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132 rgb segment & 162 common driver for 65,536 color stn lcd mar. 08, 2004 ver. 1.5 prepared by checked by approved by sunam, park ray.park@samsung.com jeahoon.lee jhoon.lee@samsung.com yhong-deug, ma yd.ma@samsung.com system lsi division semiconductor business samsung electronics co., ltd.
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 2 co ntents introduction................................................................................................................... ......................................1 features....................................................................................................................... ..........................................1 block diagram .................................................................................................................. ...................................2 pad configuration .............................................................................................................. ...............................3 pin configuration.............................................................................................................. .................................4 pin configuration.............................................................................................................. .................................5 pad center coordinates ......................................................................................................... ........................6 pin description................................................................................................................ ...................................12 functional description ......................................................................................................... ........................15 mpu interface .................................................................................................................. ...........................15 display data ram............................................................................................................... .........................19 instruction description........................................................................................................ ........................28 instruction parameter.......................................................................................................... ........................57 power on/off seqence ........................................................................................................... ........................60 specifications ................................................................................................................. ...................................62 absolute maximum ratings....................................................................................................... .............62 operating voltage .............................................................................................................. .....................62 dc characteristics (1)......................................................................................................... ....................63 dc characteristics (2)......................................................................................................... ....................64 dc characteristics (3)......................................................................................................... ....................65 dc characteristics (4)......................................................................................................... ....................66 dc characteristics (5)......................................................................................................... ....................67 ac characteristics ............................................................................................................. .....................68 series specifications.......................................................................................................... ............................71 system application diagram..................................................................................................... ...................72 otp calibration mode ........................................................................................................... ..........................74 sequence for setting the modified electronic volume .........................................................74 eprom cell structure ........................................................................................................... .................75 v1out calibration flow ......................................................................................................... .................75 voltages and waveforms for otp programming .......................................................................76 revision history ............................................................................................................... .................................77
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 1 introduction s6b33b2 is a mid-display-size-compatible driver for liquid crystal dot matrix gray-scale graphic systems. with on- chip cr oscillator circuit, the display-timing signal is ge nerated without being sent from mpu. also, it is capable of using 8bit/16bit data bus alternatively and operating wi th 68/80-series mpu in asynchronous. due to the lcd driving signal (132 rgb x 162 output) corresponding to the display data and the internal bit-map display ram of 132 163 16-bit, s6b33b2 is capable of operating max. 132 rg b x 162 dot lcd panels in low-power consumption. being the segment rgb 3-output, one pixel is 16-bit data and s6b33b2 can max display 65,536 color. features driver output ? 132 rgb x 162 gray scale function ? 65,536 color display of r: 32 gray scale, g: 64 gray scale, b: 32 gray scale ? 4,096 color display of r: 16 gray scale, g: 16 gray scale, b: 16 gray scale ? 256 color display of r: 8 gray scale, g: 8 gray scale, b: 4 gray scale on-chip display data ram ? capacity: 132 x 16 x 162 = 342.144k bits ? burst ram write function display mode ? normal display mode: entire duty displaying, partial display mode: partial duty displaying ? area scroll mode: particular area scrolling, standby mode: internal display clocks off microprocessor interface ? 8-bit/16 bit parallel bi-directional interface with 6800-series or 8080-series ? 3/4 pin spi (only write operation) on-chip low power analog circuit ? on-chip cr oscillator (internal cap. & ex ternal resistor), external clock available ? voltage converter / voltage regulator / voltage follower ? on-chip electronic contrast control (256 steps) operating voltage range ? vdd : 1.8 to 3.3 [v] (without internal regulator), 2.4 to 3.3 [v] (with internal regulator) ? vin1: 2.4 to 3.6 [v] ? display operating voltage(v1): 2.0 to 4.0 v ? lcd operating voltage range : max. 20 v low power consumption ? 750 a typ. (refer to dc characteristics (2)) package type cog (output pad pitch min. 40 m) special features ? non-volatile memory for v1 calibration
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 2 block diagram com driving circuit lcd system control circuit bus holder mpu interface cs2 cs1b db<15:0> display data ram 162 x 2112 mpu system control circuit instruction decoder seg driving circuit y - address control circuit i/o buffer x - address control circuit status oscillator circuit voltage converter/ voltage regulator/ voltage follower ps rstb vrn vmin vrp v1in reg_enb reg_out power regulator circuit decoder circuit 2112 396 162 pm fr cl vss vee vcc vin2 vin45 vout45 c11p c11m c12m c12p vin1 v1t c21p c22m c22p c21m c23p c23m c24p c24m c31p c31m intrs vdd3, vdd3r vdd,vddo v0in vmout v1out osc5 osc2 osc3 osc4 osc1 sega0 segb0 - - - segc0 com0 - - - com161 sega131 segb131 segc131 dc2out dc2in mpu[1:0] wrb d/i(rs) rdb cdir vss,vssa,vssb,vsso otpd otpg otp cell figure 1. block diagram
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 3 pad configuration ....................... ............ x y (0,0) pad 739 1 214 256 215 255 780 740 tom a lign ke y s6b33b2 figure 2. s6b33b2 chip pad configuration table 1. s6b33b2 pad dimensions size item pad no. xy unit chip size (with s/l 120 m) 19960 2130 1 to 214 90 pad pitch 215 to 780 40 1 to 214 70 70 215 to 255, 740 to 780 150 25 bumped pad size 256 to 739 25 150 bumped pad height all pad 17 m
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 4 cog align key coordinate ilb align key coordinate 30 m30 m30 m 30 m30 m30 m 30 m30 m30 m 60 m 30 m (8018,-526) (8018,-393) 19 m81 m 19 m81 m (-9881.5,968.5) 19 m 81 m 19 m 81 m (8254.5,-535.5) figure 3. cog align key coordinate figure 4. ilb align key coordinate tom(teg on main chip) coordinate cof align key coordinate 70um 70um 70um (-9456,745) (-9526,675) (9529,745) (9459,675) 50um 20um 220um (8897,-357) (9477,-577) 580um 220um (8300,-357) (8880,-577) 580um 220um (-8731,-359) (-8151,-579) 580um
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 5 pin configuration com0 com1 com2 com36 com37 com38 : : : : : : : : : : : : segc0 segb0 sega0 segc1 segb1 sega1 segc2 segb2 sega2 : : : : : : : : : : : : : : : : : : : : : : : segc129 segb129 sega129 segc130 segb130 sega130 segc131 segb131 sega131 s6b33b2 (top view) c21m c21p dc2in dc2out vmin vmout v1t v1out v1in c12m c12p c11m c11p vout45 vin45 vin2 vin1(vin1a) vdd1(vdd3=vdd3r) reg_out vdd(vddo) osc1 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 osc2 osc3 osc4 osc5 intrs reg_enb vss db0 rdb wrb rs rstb pm fr cl test[0] cs2 cs1b cdir mpu0 mpu1 ps voin c22m c22p c23m c23p c24m c24p vee vrn vrp vcc c31m c31p voin com81 com82 com83 com117 com118 com119 : : : : : : : : : : : : : : : com39 com40 com41 com78 com79 com80 : : : com161 com161 com161 com122 com121 com120 : : : otpg otpd test[1] test[2] test[3] test[4] test[5] test[6] dmy_test<0:1> dmy_test<2:3> figure 5. s6b33b2 chip pin configuration
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 6 pad center coordinates table 2. pad center coordinates [unit: m] no x y name no x y name no x y name 1 -9585 -950 dmy_test<0> 51 -5085 -950 db<12> 101 -585 -950 vdd3r 2 -9495 -950 dmy_test<1> 52 -4995 -950 db<13> 102 -495 -950 vdd3r 3 -9405 -950 v0in 53 -4905 -950 db<14> 103 -405 -950 vdd3 4 -9315 -950 v0in 54 -4815 -950 db<15> 104 -315 -950 vdd3 5 -9225 -950 v0in 55 -4725 -950 vss 105 -225 -950 vdd3 6 -9135 -950 vss 56 -4635 -950 vss 106 -135 -950 vdd3 7 -9045 -950 ps 57 -4545 -950 vss 107 -45 -950 vin1a 8 -8955 -950 vdd3 58 -4455 -950 vss 108 45 -950 vin1a 9 -8865 -950 mpu<1> 59 -4365 -950 vss 109 135 -950 vin1a 10 -8775 -950 vss 60 -4275 -950 vss 110 225 -950 vin1a 11 -8685 -950 mpu<0> 61 -4185 -950 vss 111 315 -950 vin1 12 -8595 -950 vdd3 62 -4095 -950 vss 112 405 -950 vin1 13 -8505 -950 cdir 63 -4005 -950 vssa 113 495 -950 vin1 14 -8415 -950 vss 64 -3915 -950 vssa 114 585 -950 vin1 15 -8325 -950 cs1b 65 -3825 -950 vssa 115 675 -950 vin1 16 -8235 -950 cs2 66 -3735 -950 vssa 116 765 -950 vin1 17 -8145 -950 vdd3 67 -3645 -950 vsso 117 855 -950 vin1 18 -8055 -950 otpd 68 -3555 -950 vsso 118 945 -950 vin1 19 -7965 -950 otpd 69 -3465 -950 vssb 119 1035 -950 vin2 20 -7875 -950 otpg 70 -3375 -950 vssb 120 1125 -950 vin2 21 -7785 -950 otpg 71 -3285 -950 vssb 121 1215 -950 vin2 22 -7695 -950 test<6> 72 -3195 -950 vssb 122 1305 -950 vin2 23 -7605 -950 test<5> 73 -3105 -950 vssb 123 1395 -950 vin45 24 -7515 -950 test<4> 74 -3015 -950 vssb 124 1485 -950 vin45 25 -7425 -950 test<3> 75 -2925 -950 vssb 125 1575 -950 vin45 26 -7335 -950 test<2> 76 -2835 -950 vssb 126 1665 -950 vout45 27 -7245 -950 test<1> 77 -2745 -950 reg_enb 127 1755 -950 vout45 28 -7155 -950 test<0> 78 -2655 -950 vdd3 128 1845 -950 vout45 29 -7065 -950 vdd3 79 -2565 -950 intrs 129 1935 -950 c11p 30 -6975 -950 cl 80 -2475 -950 osc5 130 2025 -950 c11p 31 -6885 -950 fr 81 -2385 -950 vss 131 2115 -950 c11p 32 -6795 -950 pm 82 -2295 -950 osc4 132 2205 -950 c11m 33 -6705 -950 rstb 83 -2205 -950 osc3 133 2295 -950 c11m 34 -6615 -950 rs 84 -2115 -950 osc2 134 2385 -950 c11m 35 -6525 -950 vss 85 -2025 -950 osc1 135 2475 -950 c12p 36 -6435 -950 wrb 86 -1935 -950 reg_out 136 2565 -950 c12p 37 -6345 -950 rdb 87 -1845 -950 reg_out 137 2655 -950 c12p 38 -6255 -950 vdd3 88 -1755 -950 reg_out 138 2745 -950 c12m 39 -6165 -950 db<0> 89 -1665 -950 reg_out 139 2835 -950 c12m 40 -6075 -950 db<1> 90 -1575 -950 vddo 140 2925 -950 c12m 41 -5985 -950 db<2> 91 -1485 -950 vddo 141 3015 -950 v1in 42 -5895 -950 db<3> 92 -1395 -950 vdd 142 3105 -950 v1in 43 -5805 -950 db<4> 93 -1305 -950 vdd 143 3195 -950 v1in 44 -5715 -950 db<5> 94 -1215 -950 vdd 144 3285 -950 v1out 45 -5625 -950 db<6> 95 -1125 -950 vdd 145 3375 -950 v1out 46 -5535 -950 db<7> 96 -1035 -950 vdd 146 3465 -950 v1out 47 -5445 -950 db<8> 97 -945 -950 vdd 147 3555 -950 v1t 48 -5355 -950 db<9> 98 -855 -950 vdd 148 3645 -950 v1t 49 -5265 -950 db<10> 99 -765 -950 vdd3r 149 3735 -950 vmout 50 -5175 -950 db<11> 100 -675 -950 vdd3r 150 3825 -950 vmout
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 7 table 2. pad center coordinates (continued) [unit: m] no x y name no x y name no x y name 151 3915 -950 vmout 201 8415 -950 vrp 251 9824 618 com<35> 152 4005 -950 vmout 202 8505 -950 c31p 252 9824 658 com<36> 153 4095 -950 vmin 203 8595 -950 c31p 253 9824 698 com<37> 154 4185 -950 vmin 204 8685 -950 c31p 254 9824 738 com<38> 155 4275 -950 vmin 205 8775 -950 c31m 255 9824 778 dummy<1> 156 4365 -950 vmin 206 8865 -950 c31m 256 9660 910 dummy<2> 157 4455 -950 dc2out 207 8955 -950 c31m 257 9620 910 com<39> 158 4545 -950 dc2out 208 9045 -950 d ummy< 12 > 258 9580 910 com<40> 159 4635 -950 dc2out 209 9135 -950 vss 259 9540 910 com<41> 160 4725 -950 dc2in 210 9225 -950 v0in 260 9500 910 com<42> 161 4815 -950 dc2in 211 9315 -950 v0in 261 9460 910 com<43> 162 4905 -950 dc2in 212 9405 -950 v0in 262 9420 910 com<44> 163 4995 -950 c21p 213 9495 -950 dmy_test<2> 263 9380 910 com<45> 164 5085 -950 c21p 214 9585 -950 dmy_test<3> 264 9340 910 com<46> 165 5175 -950 c21p 215 9824 -822 dummy<0> 265 9300 910 com<47> 166 5265 -950 c21m 216 9824 -782 com<0> 266 9260 910 com<48> 167 5355 -950 c21m 217 9824 -742 com<1> 267 9220 910 com<49> 168 5445 -950 c21m 218 9824 -702 com<2> 268 9180 910 com<50> 169 5535 -950 c22p 219 9824 -662 com<3> 269 9140 910 com<51> 170 5625 -950 c22p 220 9824 -622 com<4> 270 9100 910 com<52> 171 5715 -950 c22p 221 9824 -582 com<5> 271 9060 910 com<53> 172 5805 -950 c22m 222 9824 -542 com<6> 272 9020 910 com<54> 173 5895 -950 c22m 223 9824 -502 com<7> 273 8980 910 com<55> 174 5985 -950 c22m 224 9824 -462 com<8> 274 8940 910 com<56> 175 6075 -950 c23p 225 9824 -422 com<9> 275 8900 910 com<57> 176 6165 -950 c23p 226 9824 -382 com<10> 276 8860 910 com<58> 177 6255 -950 c23p 227 9824 -342 com<11> 277 8820 910 com<59> 178 6345 -950 c23m 228 9824 -302 com<12> 278 8780 910 com<60> 179 6435 -950 c23m 229 9824 -262 com<13> 279 8740 910 com<61> 180 6525 -950 c23m 230 9824 -222 com<14> 280 8700 910 com<62> 181 6615 -950 c24p 231 9824 -182 com<15> 281 8660 910 com<63> 182 6705 -950 c24p 232 9824 -142 com<16> 282 8620 910 com<64> 183 6795 -950 c24p 233 9824 -102 com<17> 283 8580 910 com<65> 184 6885 -950 c24m 234 9824 -62 com<18> 284 8540 910 com<66> 185 6975 -950 c24m 235 9824 -22 com<19> 285 8500 910 com<67> 186 7065 -950 c24m 236 9824 18 com<20> 286 8460 910 com<68> 187 7155 -950 vrn 237 9824 58 com<21> 287 8420 910 com<69> 188 7245 -950 vrn 238 9824 98 com<22> 288 8380 910 com<70> 189 7335 -950 vrn 239 9824 138 com<23> 289 8340 910 com<71> 190 7425 -950 vee 240 9824 178 com<24> 290 8300 910 com<72> 191 7515 -950 vee 241 9824 218 com<25> 291 8260 910 com<73> 192 7605 -950 vee 242 9824 258 com<26> 292 8220 910 com<74> 193 7695 -950 vee 243 9824 298 com<27> 293 8180 910 com<75> 194 7785 -950 d ummy< 10 > 244 9824 338 com<28> 294 8140 910 com<76> 195 7875 -950 d ummy< 11 > 245 9824 378 com<29> 295 8100 910 com<77> 196 7965 -950 vcc 246 9824 418 com<30> 296 8060 910 com<78> 197 8055 -950 vcc 247 9824 458 com<31> 297 8020 910 com<79> 198 8145 -950 vcc 248 9824 498 com<32> 298 7980 910 com<80> 199 8235 -950 vrp 249 9824 538 com<33> 299 7940 910 dummy<3> 200 8325 -950 vrp 250 9824 578 com<34> 300 7900 910 segc<0>
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 8 table 2. pad center coordinates (continued) [unit: m] no x y name no x y name no x y name 301 7860 910 segb<0> 351 5860 910 segc<17> 401 3860 910 sega<33> 302 7820 910 sega<0> 352 5820 910 segb<17> 402 3820 910 segc<34> 303 7780 910 segc<1> 353 5780 910 sega<17> 403 3780 910 segb<34> 304 7740 910 segb<1> 354 5740 910 segc<18> 404 3740 910 sega<34> 305 7700 910 sega<1> 355 5700 910 segb<18> 405 3700 910 segc<35> 306 7660 910 segc<2> 356 5660 910 sega<18> 406 3660 910 segb<35> 307 7620 910 segb<2> 357 5620 910 segc<19> 407 3620 910 sega<35> 308 7580 910 sega<2> 358 5580 910 segb<19> 408 3580 910 segc<36> 309 7540 910 segc<3> 359 5540 910 sega<19> 409 3540 910 segb<36> 310 7500 910 segb<3> 360 5500 910 segc<20> 410 3500 910 sega<36> 311 7460 910 sega<3> 361 5460 910 segb<20> 411 3460 910 segc<37> 312 7420 910 segc<4> 362 5420 910 sega<20> 412 3420 910 segb<37> 313 7380 910 segb<4> 363 5380 910 segc<21> 413 3380 910 sega<37> 314 7340 910 sega<4> 364 5340 910 segb<21> 414 3340 910 segc<38> 315 7300 910 segc<5> 365 5300 910 sega<21> 415 3300 910 segb<38> 316 7260 910 segb<5> 366 5260 910 segc<22> 416 3260 910 sega<38> 317 7220 910 sega<5> 367 5220 910 segb<22> 417 3220 910 segc<39> 318 7180 910 segc<6> 368 5180 910 sega<22> 418 3180 910 segb<39> 319 7140 910 segb<6> 369 5140 910 segc<23> 419 3140 910 sega<39> 320 7100 910 sega<6> 370 5100 910 segb<23> 420 3100 910 segc<40> 321 7060 910 segc<7> 371 5060 910 sega<23> 421 3060 910 segb<40> 322 7020 910 segb<7> 372 5020 910 segc<24> 422 3020 910 sega<40> 323 6980 910 sega<7> 373 4980 910 segb<24> 423 2980 910 segc<41> 324 6940 910 segc<8> 374 4940 910 sega<24> 424 2940 910 segb<41> 325 6900 910 segb<8> 375 4900 910 segc<25> 425 2900 910 sega<41> 326 6860 910 sega<8> 376 4860 910 segb<25> 426 2860 910 segc<42> 327 6820 910 segc<9> 377 4820 910 sega<25> 427 2820 910 segb<42> 328 6780 910 segb<9> 378 4780 910 segc<26> 428 2780 910 sega<42> 329 6740 910 sega<9> 379 4740 910 segb<26> 429 2740 910 segc<43> 330 6700 910 segc<10> 380 4700 910 sega<26> 430 2700 910 segb<43> 331 6660 910 segb<10> 381 4660 910 segc<27> 431 2660 910 sega<43> 332 6620 910 sega<10> 382 4620 910 segb<27> 432 2620 910 segc<44> 333 6580 910 segc<11> 383 4580 910 sega<27> 433 2580 910 segb<44> 334 6540 910 segb<11> 384 4540 910 segc<28> 434 2540 910 sega<44> 335 6500 910 sega<11> 385 4500 910 segb<28> 435 2500 910 segc<45> 336 6460 910 segc<12> 386 4460 910 sega<28> 436 2460 910 segb<45> 337 6420 910 segb<12> 387 4420 910 segc<29> 437 2420 910 sega<45> 338 6380 910 sega<12> 388 4380 910 segb<29> 438 2380 910 segc<46> 339 6340 910 segc<13> 389 4340 910 sega<29> 439 2340 910 segb<46> 340 6300 910 segb<13> 390 4300 910 segc<30> 440 2300 910 sega<46> 341 6260 910 sega<13> 391 4260 910 segb<30> 441 2260 910 segc<47> 342 6220 910 segc<14> 392 4220 910 sega<30> 442 2220 910 segb<47> 343 6180 910 segb<14> 393 4180 910 segc<31> 443 2180 910 sega<47> 344 6140 910 sega<14> 394 4140 910 segb<31> 444 2140 910 segc<48> 345 6100 910 segc<15> 395 4100 910 sega<31> 445 2100 910 segb<48> 346 6060 910 segb<15> 396 4060 910 segc<32> 446 2060 910 sega<48> 347 6020 910 sega<15> 397 4020 910 segb<32> 447 2020 910 segc<49> 348 5980 910 segc<16> 398 3980 910 sega<32> 448 1980 910 segb<49> 349 5940 910 segb<16> 399 3940 910 segc<33> 449 1940 910 sega<49> 350 5900 910 sega<16> 400 3900 910 segb<33> 450 1900 910 segc<50>
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 9 table 2. pad center coordinates (continued) [unit: m] no x y name no x y name no x y name 451 1860 910 segb<50> 501 -140 910 segc<67> 551 -2140 910 sega<83> 452 1820 910 sega<50> 502 -180 910 segb<67> 552 -2180 910 segc<84> 453 1780 910 segc<51> 503 -220 910 sega<67> 553 -2220 910 segb<84> 454 1740 910 segb<51> 504 -260 910 segc<68> 554 -2260 910 sega<84> 455 1700 910 sega<51> 505 -300 910 segb<68> 555 -2300 910 segc<85> 456 1660 910 segc<52> 506 -340 910 sega<68> 556 -2340 910 segb<85> 457 1620 910 segb<52> 507 -380 910 segc<69> 557 -2380 910 sega<85> 458 1580 910 sega<52> 508 -420 910 segb<69> 558 -2420 910 segc<86> 459 1540 910 segc<53> 509 -460 910 sega<69> 559 -2460 910 segb<86> 460 1500 910 segb<53> 510 -500 910 segc<70> 560 -2500 910 sega<86> 461 1460 910 sega<53> 511 -540 910 segb<70> 561 -2540 910 segc<87> 462 1420 910 segc<54> 512 -580 910 sega<70> 562 -2580 910 segb<87> 463 1380 910 segb<54> 513 -620 910 segc<71> 563 -2620 910 sega<87> 464 1340 910 sega<54> 514 -660 910 segb<71> 564 -2660 910 segc<88> 465 1300 910 segc<55> 515 -700 910 sega<71> 565 -2700 910 segb<88> 466 1260 910 segb<55> 516 -740 910 segc<72> 566 -2740 910 sega<88> 467 1220 910 sega<55> 517 -780 910 segb<72> 567 -2780 910 segc<89> 468 1180 910 segc<56> 518 -820 910 sega<72> 568 -2820 910 segb<89> 469 1140 910 segb<56> 519 -860 910 segc<73> 569 -2860 910 sega<89> 470 1100 910 sega<56> 520 -900 910 segb<73> 570 -2900 910 segc<90> 471 1060 910 segc<57> 521 -940 910 sega<73> 571 -2940 910 segb<90> 472 1020 910 segb<57> 522 -980 910 segc<74> 572 -2980 910 sega<90> 473 980 910 sega<57> 523 -1020 910 segb<74> 573 -3020 910 segc<91> 474 940 910 segc<58> 524 -1060 910 sega<74> 574 -3060 910 segb<91> 475 900 910 segb<58> 525 -1100 910 segc<75> 575 -3100 910 sega<91> 476 860 910 sega<58> 526 -1140 910 segb<75> 576 -3140 910 segc<92> 477 820 910 segc<59> 527 -1180 910 sega<75> 577 -3180 910 segb<92> 478 780 910 segb<59> 528 -1220 910 segc<76> 578 -3220 910 sega<92> 479 740 910 sega<59> 529 -1260 910 segb<76> 579 -3260 910 segc<93> 480 700 910 segc<60> 530 -1300 910 sega<76> 580 -3300 910 segb<93> 481 660 910 segb<60> 531 -1340 910 segc<77> 581 -3340 910 sega<93> 482 620 910 sega<60> 532 -1380 910 segb<77> 582 -3380 910 segc<94> 483 580 910 segc<61> 533 -1420 910 sega<77> 583 -3420 910 segb<94> 484 540 910 segb<61> 534 -1460 910 segc<78> 584 -3460 910 sega<94> 485 500 910 sega<61> 535 -1500 910 segb<78> 585 -3500 910 segc<95> 486 460 910 segc<62> 536 -1540 910 sega<78> 586 -3540 910 segb<95> 487 420 910 segb<62> 537 -1580 910 segc<79> 587 -3580 910 sega<95> 488 380 910 sega<62> 538 -1620 910 segb<79> 588 -3620 910 segc<96> 489 340 910 segc<63> 539 -1660 910 sega<79> 589 -3660 910 segb<96> 490 300 910 segb<63> 540 -1700 910 segc<80> 590 -3700 910 sega<96> 491 260 910 sega<63> 541 -1740 910 segb<80> 591 -3740 910 segc<97> 492 220 910 segc<64> 542 -1780 910 sega<80> 592 -3780 910 segb<97> 493 180 910 segb<64> 543 -1820 910 segc<81> 593 -3820 910 sega<97> 494 140 910 sega<64> 544 -1860 910 segb<81> 594 -3860 910 segc<98> 495 100 910 segc<65> 545 -1900 910 sega<81> 595 -3900 910 segb<98> 496 60 910 segb<65> 546 -1940 910 segc<82> 596 -3940 910 sega<98> 497 20 910 sega<65> 547 -1980 910 segb<82> 597 -3980 910 segc<99> 498 -20 910 segc<66> 548 -2020 910 sega<82> 598 -4020 910 segb<99> 499 -60 910 segb<66> 549 -2060 910 segc<83> 599 -4060 910 sega<99> 500 -100 910 sega<66> 550 -2100 910 segb<83> 600 -4100 910 s egc<100 >
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 10 table 2. pad center coordinates (continued) [unit: m] no x y name no x y name no x y name 601 -4140 910 s egb<100 > 651 -6140 910 s egc<117 > 701 -8140 910 com<157> 602 -4180 910 s ega<100 > 652 -6180 910 s egb<117 > 702 -8180 910 com<156> 603 -4220 910 s egc<101 > 653 -6220 910 s ega<117 > 703 -8220 910 com<155> 604 -4260 910 s egb<101 > 654 -6260 910 s egc<118 > 704 -8260 910 com<154> 605 -4300 910 s ega<101 > 655 -6300 910 s egb<118 > 705 -8300 910 com<153> 606 -4340 910 s egc<102 > 656 -6340 910 s ega<118 > 706 -8340 910 com<152> 607 -4380 910 s egb<102 > 657 -6380 910 s egc<119 > 707 -8380 910 com<151> 608 -4420 910 s ega<102 > 658 -6420 910 s egb<119 > 708 -8420 910 com<150> 609 -4460 910 s egc<103 > 659 -6460 910 s ega<119 > 709 -8460 910 com<149> 610 -4500 910 s egb<103 > 660 -6500 910 s egc<120 > 710 -8500 910 com<148> 611 -4540 910 s ega<103 > 661 -6540 910 s egb<120 > 711 -8540 910 com<147> 612 -4580 910 s egc<104 > 662 -6580 910 s ega<120 > 712 -8580 910 com<146> 613 -4620 910 s egb<104 > 663 -6620 910 s egc<121 > 713 -8620 910 com<145> 614 -4660 910 s ega<104 > 664 -6660 910 s egb<121 > 714 -8660 910 com<144> 615 -4700 910 s egc<105 > 665 -6700 910 s ega<121 > 715 -8700 910 com<143> 616 -4740 910 s egb<105 > 666 -6740 910 s egc<122 > 716 -8740 910 com<142> 617 -4780 910 s ega<105 > 667 -6780 910 s egb<122 > 717 -8780 910 com<141> 618 -4820 910 s egc<106 > 668 -6820 910 s ega<122 > 718 -8820 910 com<140> 619 -4860 910 s egb<106 > 669 -6860 910 s egc<123 > 719 -8860 910 com<139> 620 -4900 910 s ega<106 > 670 -6900 910 s egb<123 > 720 -8900 910 com<138> 621 -4940 910 s egc<107 > 671 -6940 910 s ega<123 > 721 -8940 910 com<137> 622 -4980 910 s egb<107 > 672 -6980 910 s egc<124 > 722 -8980 910 com<136> 623 -5020 910 s ega<107 > 673 -7020 910 s egb<124 > 723 -9020 910 com<135> 624 -5060 910 s egc<108 > 674 -7060 910 s ega<124 > 724 -9060 910 com<134> 625 -5100 910 s egb<108 > 675 -7100 910 s egc<125 > 725 -9100 910 com<133> 626 -5140 910 s ega<108 > 676 -7140 910 s egb<125 > 726 -9140 910 com<132> 627 -5180 910 s egc<109 > 677 -7180 910 s ega<125 > 727 -9180 910 com<131> 628 -5220 910 s egb<109 > 678 -7220 910 s egc<126 > 728 -9220 910 com<130> 629 -5260 910 s ega<109 > 679 -7260 910 s egb<126 > 729 -9260 910 com<129> 630 -5300 910 s egc<110 > 680 -7300 910 s ega<126 > 730 -9300 910 com<128> 631 -5340 910 s egb<110 > 681 -7340 910 s egc<127 > 731 -9340 910 com<127> 632 -5380 910 s ega<110 > 682 -7380 910 s egb<127 > 732 -9380 910 com<126> 633 -5420 910 s egc<111 > 683 -7420 910 s ega<127 > 733 -9420 910 com<125> 634 -5460 910 s egb<111 > 684 -7460 910 s egc<128 > 734 -9460 910 com<124> 635 -5500 910 s ega<111 > 685 -7500 910 s egb<128 > 735 -9500 910 com<123> 636 -5540 910 s egc<112 > 686 -7540 910 s ega<128 > 736 -9540 910 com<122> 637 -5580 910 s egb<112 > 687 -7580 910 s egc<129 > 737 -9580 910 com<121> 638 -5620 910 s ega<112 > 688 -7620 910 s egb<129 > 738 -9620 910 com<120> 639 -5660 910 s egc<113 > 689 -7660 910 s ega<129 > 739 -9660 910 dummy<5> 640 -5700 910 s egb<113 > 690 -7700 910 s egc<130 > 740 -9824 778 dummy<6> 641 -5740 910 s ega<113 > 691 -7740 910 s egb<130 > 741 -9824 738 com<119> 642 -5780 910 s egc<114 > 692 -7780 910 s ega<130 > 742 -9824 698 com<118> 643 -5820 910 s egb<114 > 693 -7820 910 s egc<131 > 743 -9824 658 com<117> 644 -5860 910 s ega<114 > 694 -7860 910 s egb<131 > 744 -9824 618 com<116> 645 -5900 910 s egc<115 > 695 -7900 910 s ega<131 > 745 -9824 578 com<115> 646 -5940 910 s egb<115 > 696 -7940 910 dummy<4> 746 -9824 538 com<114> 647 -5980 910 s ega<115 > 697 -7980 910 com<161> 747 -9824 498 com<113> 648 -6020 910 s egc<116 > 698 -8020 910 com<160> 748 -9824 458 com<112> 649 -6060 910 s egb<116 > 699 -8060 910 com<159> 749 -9824 418 com<111> 650 -6100 910 s ega<116 > 700 -8100 910 com<158> 750 -9824 378 com<110>
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 11 table 2. pad center coordinates (continued) [unit: m] no x y name 751 -9824 338 com<109> 752 -9824 298 com<108> 753 -9824 258 com<107> 754 -9824 218 com<106> 755 -9824 178 com<105> 756 -9824 138 com<104> 757 -9824 98 com<103> 758 -9824 58 com<102> 759 -9824 18 com<101> 760 -9824 -22 com<100> 761 -9824 -62 com<99> 762 -9824 -102 com<98> 763 -9824 -142 com<97> 764 -9824 -182 com<96> 765 -9824 -222 com<95> 766 -9824 -262 com<94> 767 -9824 -302 com<93> 768 -9824 -342 com<92> 769 -9824 -382 com<91> 770 -9824 -422 com<90> 771 -9824 -462 com<89> 772 -9824 -502 com<88> 773 -9824 -542 com<87> 774 -9824 -582 com<86> 775 -9824 -622 com<85> 776 -9824 -662 com<84> 777 -9824 -702 com<83> 778 -9824 -742 com<82> 779 -9824 -782 com<81> 780 -9824 -822 dummy<7>
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 12 pin description table 3. power supply pins name i/o description vdd3 supply main power supply vdd3r supply internal regulator power supply this pin is connected to vdd3. vdd supply regulated power supply input pin for internal digital and ddram block. this pin is connected to reg_out outside the chip with stabilization capacitor. when the internal regulator is not used, vdd1 should be tied to vdd directly. vddo supply internal oscillator power supply this pin is connected to vdd. vss vsso vssa vssb gnd ground v1in / v1out i / o lcd segment high selected driving voltage input / output pin vmin / vmout i / o lcd common/segment non-s elected driving voltage input / output pin v0in i lcd segment low selected driving voltage input pin vcc / vrp i / o lcd common high selected driving voltage input / output pin vee / vrn i / o lcd common low selected driving voltage input / output pin the relationship between vcc, v1, vm, v0 and vee: vcc > v1 > vm > v0(=vss) > vee (v1 - vm = vm ? v0, vcc ?vm = vm - vee) vin1 vin1a i power supply for 1?st booster circuit and vm amp vin2 i power supply for 2?nd booster circuit vout45 o 1?st booster output pin vin45 i power supply for v1. connect to vout45 or vin1 c11p c11m c12p c12m o external capacitor connection pins used for 1?st booster circuit v1t i thermistor resistor connection pin intrs i external resister select pin for temperature compensation circuit - intrs = l : external resistor mode, intrs = h : internal resistor mode dc2in i power supply for 2?nd booster. connect to dc2out pin dc2out o power output pin for 2?nd booster input c21p c21m c22p c22m c23p c23m c24p c24m o external capacitor connection pins used for 2?nd booster circuit c31p c31m o external capacitor connection pins used for 3?rd booster circuit otpg i gate voltage for otp programming otpd i drain voltage for otp programming
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 13 table 4. mpu interface pins name i/o description rstb i reset input pin. when rstb is ?l?, initialization is executed. mpu interface select pin ps mpu[1] mpu[0] description h l l 8080-series 8bit interface h l h 8080-series 16bit interface h h l 6800-series 8bit interface h h h 6800-series 16bit interface l l x 3 pin spi(write only) ps mpu[1:0] i l h x 4 pin spi(write only) cs1b cs2 i chip select input pins data / instruction i/o is enabled only when cs1b is ?l? and cs2 is ?h?. when chip select is non-active, db0 to db15 may be high impedance. d/i (rs) i data / instruction select input pin ? d/i = ?h?: db0 to db15 are display data ? d/i = ?l?: db0 to db7 are instruction data read / write execution control pin ps mpu mpu type wrb description h h 6800-series r/w readwrbite control input pin ? r/w = ?h?: read ? r/w = ?l?: write wrb (r/w) i h l 8080-series wrb write enable clock input pin the data on db0 to db15 are latched at the rising edge of the wrb signal. read / write execution control pin mpu[1] mpu type rdb description h 6800- series e read / write control input pin ? r/w = ?h?: when e is ?h?, db0 to db15 are in an output status. ? r/w = ?l?: the data on db0 to db15 are latched at the falling edge of the e signal. rdb (e) i l 8080- series rdb read enable clock input pin when rdb is ?l?, db0 to db15 are in an output status. db[15:8] db[7]/sdi db[6]/scl db[5:0] i/o -db[15:0]: 16-bit bi-directional data bus. -sdi: serial data input pin. the dat a is latched at the rising edge of scl. -scl: serial clock input pin. cdir i common direction select pin.
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 14 table 5. oscillator and power regulator pins name i/o description osc1 osc2 osc3 osc4 o cr oscillator output pin when the internal cr oscillator is used, connect to osc1, osc3 through a resistor. osc1 ? osc2: using in normal display mode, partial display mode 0 osc3 ? osc4: using in partial display mode 1 when an external oscillator is used, os c1 pin is connected to vdd or vss. osc5 i external clock input pin when an external input is used, it is input to this pin. but t he internal oscillator is used, this pin is connected to vdd3 or vss. reg_enb i internal regulator enable/disable input pin - reg_enb = ?l? (tied to vss) : enable internal regulator - reg_enb = ?h? (tied to vdd3) : disable internal regulator reg_out o internal voltage regulator output pin the regulator output port from this pin is used as a power supplier for an internal digital block via vdd pins. table 6. timing signal pins for monitoring name i/o description cl o shift clock output pin pm o field delimiter output pin fr o liquid crystal alternating current output pin table 7. lcd driver output pins name i/o description sega0 to 131 o lcd driving segment output (red or blue) segb0 to 131 o lcd driving segment output (green) segc0 to131 o lcd driving segment output (blue or red) com0 to 161 o lcd common outputs table 8. test pins name i/o description test[3:0] i don?t use these pins. ic maker?s test pins these pins must be tied to vdd3 or vss. test[6:4] o don?t use these pins. ic maker?s test pins these pins must be open. dmy_test<3:0> o don?t use these pins. ic maker?s test pins these pins must be open.
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 15 functional description mpu interface chip select input there are cs1b and cs2 pins for chip selection. the s6b33b2 can interface with an mpu only when cs1b is ?l? and cs2 is ?h?. when these pins are set to any other combination, d/i, rdb , and wrb inputs ar e disabled and db0 to db15 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel/seria l interface the s6b33b2 has four types of interfac e with an mpu, which are two serial and two parallel interfaces. this parallel or serial interface is determined by ps pin as shown in table9. table 9. parallel / seri al interface mode. ps mpu[1] cs1b cs2 mpu bus type l 8080-series mpu h h cs1b cs2 6800-series mpu l 3?pin spi l h cs1b cs2 4-pin spi parallel interface (ps=?h?) the 8-bit/16-bit bi-directional data bus is used in parallel interface. the type of mpu is selected by mpu[1] and the mode of data-bus is controlled by mpu[0] as shown in below. in accessing internal registers (d/i = ?l?), only db[7:0] are valid. table 10. microprocessor selection for parallel interface mpu[1] mpu[0] cs1b cs2 rdb wrb data bus mpu bus type l db[7:0] l h cs1b cs2 rdb wrb db[15:0] 8080-series mpu l db[7:0] h h cs1b cs2 e r/w db[15:0] 6800-series mpu table 11. parallel data transfer 6800-series 8080-series d/i rdb wrb rdb wrb description h h h l h read display data h h l h l write display data l h h l h read out internal status register l h l h l write instruction data
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 16 /cs1 cs2 d/i r/w e db command write data write status read data read figure 6. 6800-series mpu interface protocol (mpu[1]=?h?) /cs1 cs2 d/i /wr /rd db command write data write status read data read figure 7. 8080-series mpu interface protocol (mpu[1]=?l?)
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 17 serial interface(ps=?l?) communication with the microprocessor occurs via a clock-synchronized serial peripheral interface when ps is low. when using the serial interface, read operations are not allowed. when the chip select inputs are valid (cs1b = ?l? & cs2 = ?h?), the serial data is sent most significant bi t first on the rising edge of a serial clock going into db6 and processed as 8 bit parallel data on the eighth clock. since the clock signal is easy to be affected by the external noise caused by the line length, t he operation check on the actual machine is recommended. and invalid, the internal shift register and the counter are reset. the serial interface type is selected by setting ps as shown in table12. table 12. microprocessor se lection for serial interface ps mpu[1] cs1b cs2 d/i serial data serial clock spi mode l cs1b cs2 by s/w 3-pin l h cs1b cs2 d/i db[7] db[6] 4-pin 3-pin spi interface (ps = "l" & mpu[1] = "l") in 3-pin spi interface mode, the pre-defined instruction calle d display data length is used to indicate whether serial data input is display or instruction data instead of d/i pin. the data is handled as in struction data until the display data length instruction is issued. this display data length instruction consists of three bytes instruction. the first byte instruction enables the next instru ction to be valid, and data of the second two bytes indicate that a specified number of display data bytes(1 to 65536) are to be transmitted. next two bytes after the display data string is handled as instruction data. for details, refer the figure 8. chip select scl(db6) sdi(db7) internal d/i /cs1 = l, cs2 = h 1 24 ddl_h ddl_l 2 23 1 2 160 159 10 pixel display data ddl_l = 09h user's display data (max. 42768(162x132) bytes) 20 bytes(2) 3 bytes (1) ddc ddl_h = 00h ddl = 0009h(9d) (1) set ddc(display data command) and ddl(display data length) set ddc(3 pin spi mode only) : 1 1 1 1 1 1 0 0 (fch) set ddl(2 bytes) : (1'st byte) d7 d6 d5 d4 d3 d2 d1 d0 (ddl_l) (2'nd byte) d7 d6 d5 d4 d3 d2 d1 d0 (ddl_h) (2) ddl register value number of display data : (ddl + 1) pixel data ((ddl+1) x 2 byte) necessary clock pulse number : 8 x [(ddl+1) x 2] figure 8. 3-pin spi timing (d/i is not used)
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 18 4-pin serial interface (ps=?l? & mpu[1]=?h?) in 4-pin spi interface mode, d/i pin is used for indicating whether serial data input is display or instruction data. data is display data when d/i is high and instruction data when d/i is low. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. l chip select sid(db7) scl(db6) d/i db0 db1 db4 db6 db7 db3 /cs1=l, cs2=h db5 db2 db7 db6 figure 9. 4-pin serial interface timing
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 19 display data ram the on-chip display data ram of s6b33b2 is a static ram that is stored the data for the display. it is a 2,304 x 176 structure. it is controlled by 2 addresses, x and y. a nd, ram area selection and automatic address count up functions are accomplished by the internal instructions. ddram address area selection a part of ddram address area of s6b33b2 can be accessed by x and y address area settings. after setting ram area, the addresses become the start address. x-address y-address figure 10. ddram address area table 13. x address control db7 db6 db5 db4 db3 db2 db1 db0 code 00100001 p1 x start address set(initial status = 00h) p2 x end address set(initial status = a1h) table 14. y address control db7 db6 db5 db4 db3 db2 db1 db0 code 00110001 p1 y start address set (initial status = 00h) p2 y end address set (initial status =83h)
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 20 ram addressing count up by selecting the x address and y address area by the internal instructions, the address counts up from its start address to end address after data access operation. when one address is equal to the end address, it returns to the start address. at this time, the other address is increased by 1. y address count mode (y address = 00h to 83h, x address = 00h to a1h) y-address 1 2 3 4 5 6 7 8 9 00h 01h 02h 03h 04h 05h 07h 08h 06h x-address 00h 01h 02h 03h a1h 133 265 21253 132 83h 264 396 528 21384 397 figure 11. y address count mode x address count mode (y address =00h to 83h, x address = 00h to a1h) y-address 1 163 325 487 649 781 943 1105 126 7 21223 00h 01h 02h 03h 04h 05h 83h 07h 08h 06h x-address 00h 01h 02h 03h a1h 2 3 4 162 324 486 648 780 942 1104 126 6 142 8 21384 figure 12. x address count mode
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 21 xa address ya address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 00h 01h 02h 03h 04h 05h 06h 07h 7dh 7eh 7fh 80h 81h 82h 83h 08h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - b2h b3h b4h b5h b6h b7h b8h b9h bah bbh bch bdh beh bfh a0h a1h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----- ----- d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 red green blue figure 13. display data ram map
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 22 partial display mode the s6b33b2 realizes the partial display function with low duty driving for saving power consumption and showing the various display duties. it is set as display start/end line number. area scroll function the s6b33b2 realizes the specific area scroll function. (1/162 duty case). 0 15 147 161 fixed area scroll area display area lcd panel fixed 15 lines 132 lines 14 fixed 15 lines 0 146 147 161 14 example of scrolling down example of scrolling up 15 figure 14. area scroll examples (dut y = 1/162, center scroll mode)
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 23 display direction sdir the sdir flag of driver output mode set instruc tion selects the direction of segment display. x = 0 y = 1 y = 131 y = 0 sega0 segb0 segc0 sega1 segb1 segc1 sega131 segb131 segc131 (d7~d0) (d7~d0) (d7~d0) (d7~d0) (d7~d0) (d7~d0) 1st 2nd figure 15. 8-bit data bus mode when sdir = l y = 1 y = 131 y = 0 sega0 segb0 segc0 sega1 segb1 segc1 sega131 segb131 segc131 (d15~d0) (d15~d0) (d15~d0) x=0 figure 16. 16-bit data bus mode when sdir = l x = 0 y = 130 y = 0 y = 131 sega0 segb0 segc0 sega1 segb1 segc1 sega131 segb131 segc131 (d7~d0) (d7~d0) (d7~d0) (d7~d0) (d7~d0) (d7~d0) 1st 2nd figure 17. 8-bit data bus mode when sdir = h y = 130 y = 0 y = 131 sega0 segb0 segc0 sega1 segb1 segc1 sega131 segb131 segc131 (d15~d0) (d15~d0) (d15~d0) x = 0 figure 18. 16-bit data bus mode when sdir = h
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 24 cdir the direction of common scanning is selected by cdir pin. com 0 com 65 line number 0 line number 65 line number 66 display area 132 display lines (dln=00) display area com 81 com 146 line number 131 com 0 com 65 line number 131 line number 66 line number 65 display area display area com 81 com 146 line number 0 com 0 com 71 line number 0 line number 71 line number 72 display area 144 display lines (dln=01) display area com 81 com 152 line number 143 com 0 com 71 line number 143 line number 72 line number 71 display area display area com 81 com 152 line number 0 com 0 line number 0 display area 162 display lines (dln=10) com 161 line number 161 com 0 line number 161 display area com 161 line number 0 com 0 com 47 line number 0 line number 47 line number 48 display area 96 display lines (dln=11) display area com 81 com 128 line number 95 com 0 com 47 line number 95 line number 48 line number 47 display area display area com 81 line number 0 com 128 driver seg132 com162 com 80 com 0 com81
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 25 swp the swp flag of driver output mode set instruction selects the swapping of segment display. segai segbi segci red green blue color swp = 0 d15 ~ d11 d10~ d5 d4 ~ d0 assigned bit blue green red color swp = 1 d4~ d0 d10 ~ d5 d15 ~ d11 assigned bit figure 19. the relationship between seg outputs and rgb color swp=1 * i = 0 to 131 r control b control g control d15 d14 d12 d11 d9 d8 d6 d5 d4 d3 d2 d0 ram data swp=0 * i = 0 to 131 b control r control g control segai segbi segci d4 d3 d1 d0 d9 d8 d7 d5 d15 d14 d13 d11 mpu i/f data ram data mpu i/f data segai segbi segci d2 d13 d10 d6 d12 d10 d7 d1 d15 d14 d12 d11 d9 d8 d6 d5 d4 d3 d2 d0 d13 d10 d7 d1 d15 d14 d12 d11 d9 d8 d6 d5 d4 d3 d2 d0 d13 d10 d7 d1
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 26 on-chip regulator configuration the output voltage of regulator circuit(reg_out) is ranging from 1.8v to 2.2v and nominal value is 2.0v. reg_enb reg_out vdd /vddo vdd3 /vdd3r c1 vdd3 reg_enb reg_out floating vdd3 vdd3 value of external capacitance item value unit c1 1.0 to 4.7 f vdd3: 2.4 to 3.3v reg_out : 2.0v vdd3: 1.8 to 3.3v vdd /vddo vdd3 /vdd3r figure 20. regulator application oscillator circuit when internal oscillator is used(ext=0), the selection of oscillator resistor is determined by display mode. - normal display mode/ partial display mode 0 : resistor1 between osc1 and osc2 - partial display mode 1 : resistor2 between osc3 and osc4 when external clock is used (ext=1), clock frequency should be adjusted to display mode that is selected . example of external oscillator application osc4 osc2 osc3 osc5 external clock osc1 vss figure 21. external o scillator application
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 27 example of internal oscillator application osc4 osc2 osc3 r1 osc5 vss/vdd3 osc1 osc4 osc2 osc3 osc5 osc1 vss/vdd3 r2 r1 when partial display mode 1 is not used. when partial display mode 1 is used. figure 22. internal oscillator application discharge circuit driving voltage level discharge time at standby on. the relation between voltage level and discharge time from when ?standby on? command is inputted. level condition t[ms] ? v+, ? v-[mv] 100 < 50 +vr,v1,vm,-vr +vr=12.0v, v1=3.0v, vm=1.5v, -vr=-9.0v at t=0 300 < 20 vm vss -vr v1 +vr internal stb signal t[ms] v+[mv] v-[mv]
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 28 instruction description table 15. instruction table instruction name d/i wrb rdb db15 ~ db8 db7 db6 db5 db4 db3 db2 db1 db0 hex. parameter non operation 0 0 1 * 0 0 00000000 oscillation mode set 0 0 1 * 0 0 00001002 1byte driver output mode set 001 *0001000010 1byte dc-dc select 001 *0010000020 1byte bias set 001 *0010001022 1byte dcdc clock division set 0 0 1 * 0 0 10010024 1byte dcdc and amp on/off set 0 0 1 * 0 0 10011026 1byte temperature compensation set 0 0 1 * 0 0 10100028 1byte contrast control(1) 001 *001010102a 1byte contrast control(2) 001 *001010112b 1byte standby mode off 0 0 1 * 0 0 1011002c - standby mode on 0 0 1 * 0 0 1011012d - ddram burst mode off 0 0 1 * 0 0 1011102e - ddram burst mode on 0 0 1 * 0 0 1011112f - addressing mode set 0 0 1 * 0 0 11000030 1byte row vector mode set 001 *0011001032 1byte n-line inversion set 001 *0011010034 1byte frame frequency control 001 *0011011036 1byte entry mode set 0 0 1 * 0 1 00000040 1byte x-address area set 0 0 1 * 0 1 00001042 2byte y-address area set 0 0 1 * 0 1 00001143 2byte ram skip area set 0 0 1 * 0 1 00010145 1byte display off 001 *0101000050 - display on 001 *0101000151 - specified display pattern set 0 0 1 * 0 1 01001153 1byte partial display mode set 0 0 1 * 0 1 01010155 1byte partial display start line set 001 *0101011056 1byte partial display end line set 001 *0101011157 1byte area scroll mode set 0 0 1 * 0 1 01100159 4byte scroll start line set 001 *010110105a 1byte set display data length x x x * 1 1 111100fc 1byte display data write 1 0 1 display data write - - display data read 1 1 0 display data read - - status read 0 1 0 0 status data read - - test mode1 0 0 1 * 1 1 111111ff 1byte test mode2 0 0 1 * 1 1 111110fe 1byte test mode3 0 0 1 * 1 1 111101fd 1byte test mode4 0 0 1 * 1 1 111011fb 1byte test mode5 0 0 1 * 1 1 111010fa 1byte test mode6 0 0 1 * 1 1 111001f9 1byte otp mode off 001 *11101010ea - otp mode on 001 *11101011eb - offset volume set 001 *11101101ed 1byte otp write enable 001 *11101111ef - *: don?t care parameter: the number of parameter bytes that follows instruction data.
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 29 non operation (00h) this instruction is non operation. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00100000000 oscillation mode set (02h) setting internal function mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00000010 001 000000extosc ext: external clock selecting ext = 0: internal clock mode (initial status) ext = 1: external clock mode osc: internal os cillator on/off osc = 0: internal oscilla tor off(initial status) osc = 1: internal oscillator on driver output mode set(10h) this instruction sets the display direction. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00010000 001 0 0 dln 0 sdir swp 0 dln: display line number selecting db5 db4 display duty 0 0 1/132 (initial status) 01 1/144 10 1/162 11 1/96 sdir: segment direction this bit is for controlling the direction of segment driver. sdir = 0 (initial status) swp: swap segment output segai and segci this bit is for swapping the output of segment driver. swp = 0 (initial status)
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 30 dc-dc select (20h) selects dc-dc step-up of the common driver in normal and partial mode d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00100000 001 0000 dc(2) dc(1) dc(1) : 1?st dc-dc booster boosting step select for v1 generation in normal mode and partial mode 0. dc(2) : 1?st dc-dc booster boosting step select for v1 generation in partial mode 1. dc(2) : in partial mode 1 dc(1) : in normal mode, partial mode 0 db3 db2 dc-dc step up db1 db0 dc-dc step up 0 0 x1.0 0 0 x1.0 0 1 x1.5 0 1 x1.5 1 0 x2.0 1 0 x2.0 1 1 x2.0 1 1 x2.0
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 31 dc-dc select and power supply for v1 op-amp. even if vin45 is connected to vout45 or vin1, a setup by software must be able to be performed. power supply for v1 op-amp. is decided by hardware setting and software setting. the example of usage is shown below. hardware setting : vin45 connected to (1) vin1 (when 1?st boosting is not used) (2) vout45 (when 1?st boosting is used) software setting : dc-dc se lect(20h) - dc(1), dc(2) set value ?00? power supply for v1 op-amp. uses vin1 directly. set value ?01? or ?10? power supply for v1 op-amp. uses vout45. 1st booster circuit reference voltage generator & temperature compensation control circuit vin1 v1 + c11- c11+ c12- c12+ vout45 vin45 - r1 ev_256 r1 software setting hardware setting v1 generation circuit figure28. example : hardware setting software setting : vin45 connected to vout45 : power supply for v1 op.amp. uses vin1 ( not vout45). vss
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 32 bias set (22h) this instruction set up the value of bi as in normal mode and in partial mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00 1 0 00 1 0 001 0 0 bias(2) 0 0 bias(1) bias(1): bias value selecting in normal mode and partial mode0. bias(2): bias value selecting in partial mode1. bias (2) : in partial mode 1 bias (1 ) : in normal mode, partial mode 0 db5 db4 bias(2) 2?nd boosting step db1 db0 bias(1) 2?nd boosting step 0 0 1/4 x(-3) 0 0 1/4 x(-3) 0 1 1/5 x(-4) 0 1 1/5 x(-4) 1 0 1/6 x(-4) 1 0 1/6 x(-4) 1 1 1/7 x(-5) 1 1 1/7 x(-5) dcdc clock division set(24h) this instruction sets the internal booster clock frequency. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00100100 001 0 0 div(2) 0 0 div(1) div(1) : dc-dc charge pump division ratio in normal mode display and partial display mode0 - div(1) = 10 (initial status) div(2) : division ratio in partial display mode1 - div(2) = 10 (initial status) db5 db4 div(2) db1 db0 div(1) 0 0 fpck = fosc/4 0 0 fpck = fosc/4 0 1 fpck = fosc/8 0 1 fpck = fosc/8 1 0 fpck = fosc/16 1 0 fpck = fosc/16 1 1 fpck = fosc/32 1 1 fpck = fosc/32 note: fosc = ( roundup (duty/3) + dummy) x 4 x 8 x frame frequency
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 33 dc/dc and amp on/off set (26h) this instruction set up the dc/dc and op-amp in common start up setting. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00100110 001 0000ampdcdc3dcdc2dcdc1 amp: built-in op-amp on/off. - amp=0: op-amp off (initial status) - amp=1: op-amp on dcdc1: built-in 1?st booster on/off - dcdc1= 0: 1?st booster off (initial status) - dcdc1= 1: 1?st booster on dcdc2: built-in 2?nd booster on/off - dcdc2= 0: 2?nd booster off (initial status) - dcdc2= 1: 2?nd booster on dcdc3: built-in 3?rd booster on/off - dcdc3= 0: 3?rd booster off (initial status) - dcdc3= 1: 3?rd booster on temperature compensation set (28h) this instruction sets up the driving voltage slope for temperature compensation. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00101000 001 000000 tcs tcs: temperature compensation slope set - tcs = 00 : 0.00%/degc (initial status) - tcs = 01 : -0.05%/degc - tcs = 10 : -0.10%/degc - tcs = 11 : -0.15%/degc product code temp. coefficient tcs register set * s6b33b2a01-b0cy 0.00%/ c 00 S6B33B2A02-B0CY -0.05 %/ c 01 s6b33b2a03-b0cy -0.10 %/ c 10 s6b33b2a04-b0cy -0.15 %/ c 11 * note : in case of s6b33b2a01-b0cy, sec guarantees only 0.00%/ c, not ?0.05 and ?0.10, -0.15%/ c. in case of S6B33B2A02-B0CY, sec guarantees only -0.05%/ c, not ?0.00 and ?0.1, -0.15%/ c. in case of s6b33b2a03-b0cy, sec guarantees only -0.10%/ c, not ?0.00 and ?0.05, -0.15%/ c. in case of s6b33b2a04-b0cy, sec guarantees only -0.15%/ c, not ?0.00 and ?0.05, -0.10%/ c.
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 34 temperature compensation if external temperature compensation is needed, circuit diagram is described as below. to use temperature compensation, two resistors and one thermistor are needed. 00: 0.00 %/degc driving voltage 01: -0.05 %/degc 10: -0.10 %/degc 11: -0.15 %/degc temperature 25degc external chip internal v1in + - v1out v1t intrs
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 35 contrast control (1) (2ah) this instruction updates the contrast control val ue in normal display mode and partial display mode 0. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00 1 010 1 0 001 contrast control value (0 to 255) the relation between v1 voltage (typ.) and c ontrast(1) set value ( 3bit step case) contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] 00h 2.000 30h 2.376 60h 2.753 90h 3.129 c0h 3.506 f0h 3.882 08h 2.063 38h 2.439 68h 2.816 98h 3.192 c8h 3.569 f8h 3.945 10h 2.125 40h 2.502 70h 2.878 a0h 3.255 d0h 3.631 ffh 4.000 18h 2.188 48h 2.565 78h 2.941 a8h 3.318 d8h 3.694 20h 2.251 50h 2.627 80h 3.004 b0h 3.380 e0h 3.757 28h 2.314 58h 2.690 88h 3.067 b8h 3.443 e8h 3.820 contrast control (2) (2bh) this instruction updates the contrast control value in partial display mode 1. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00 1 010 1 1 001 contrast control value (0 to 255) the relation between v1 voltage (typ.) and c ontrast(2) set value ( 3 bit step case) contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] 00h 2.000 30h 2.376 60h 2.753 90h 3.129 c0h 3.506 f0h 3.882 08h 2.063 38h 2.439 68h 2.816 98h 3.192 c8h 3.569 f8h 3.945 10h 2.125 40h 2.502 70h 2.878 a0h 3.255 d0h 3.631 ffh 4.000 18h 2.188 48h 2.565 78h 2.941 a8h 3.318 d8h 3.694 20h 2.251 50h 2.627 80h 3.004 b0h 3.380 e0h 3.757 28h 2.314 58h 2.690 88h 3.067 b8h 3.443 e8h 3.820 note : s6b33b2 has a hardware protection for "2vr < 20v". it means the limitation of contrast value in each bias. if 1/6 bias is set, max contrast value is limited to a9h, and if 1/7 bias is set, max contrast value is limited to 6dh.
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 36 standby mode off (2ch) this instruction releases the standby mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00100101100 the internal statuses during standby off are as following: - all common and segment output: vss or v1 - oscillator circuit: on (ext = 0, osc=1),off (others) - displaying clocks (fr, pm, cl): in operation function and pin condition at standby off function/pin condition dc/dc booster(1?st,2?nd,3?rd) on(operate) com outputs +vr or vm or vss or -vr seg outputs v1 or vss standby mode on (2dh) this instruction enters the standby mode to reduce the power consumption to the static power consumption value (initial status). the following instructions, standby off and display on, cause returning to the normal operation status. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00100101101 the internal statuses during standby on are as following: - all common and segment output: vss - oscillator circuit: off - displaying clocks (fr, pm, cl) are held. function and pin condition at standby on function/pin condition dc/dc booster(1?st,2?nd,3?rd) off seg and com outputs vss lcd driving power output condition at standby on. level condition +vr vss v1 vss vm vss -vr vss
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 37 ddram burst mode off(2eh) /on(2fh) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0010010111bm bm: internal ddram burst mo de interface off/on control - 0 : burst mode interface off(initial status) - 1 : burst mode interface on when bm=0, if mpu[0] is 0 then internal ddram i/f bpw(bits per word) is 8 bits. else mpu[0] is 1 then internal ddram i/f bpw(bits per word) is 16bits. when bm=1, regardless of mpu[0] bit, internal ddram i/f bpw(bits per word) is 32 bits . mpu register1 00h 01h ddram x address counter 32 16 8 8 register2 02h 03h 8eh 8fh --------- y address counter 8 s6b33b2 figure 23. burst mode writing to ddram
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 38 /cs e db15 ~db0 burst mode on x address setting y address setting ram data 1(16bits) - - - - - - - - - - - - - - - - - - ram data 2(16bits) ram data 3(16bits) ram data 4(16bits) - - - - - - - - - - - - - - - ram write time ram write time ram write data (32 bits) ram data 1 to 2 ram data 3 to 4 ram data 5(16bits) ram data 6(16bits) ram write time ram data 5 to 6 ram x address ram y address 00h 00h 02h 04h - - - - - - - - - - - - - - - figure 24. example of the burst mode writing to ddram (68-mode 16-bit parallel interface) when ddram burst mode is used, note the following. notes: 1.data is written to ddram each two words. if only one word data is written to ddram, the data will not be written. so, the number of word data must be even. it means that y start address must be even and y end address must be odd. 2.x address count mode can?t be used. 3.burst mode and normal mode write operatio n cannot be executed at the same time. 4.in the read data mode and serial interface mode, the burst mode can?t be used. 5.in the 256 color mode with 16-bit data bus mode and 4,096 color mode with 8-bit data bus mode, the address is counted as burst mode enable. so these modes are influenced by above notes.
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 39 addressing mode set (30h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00110000 001 0 gsm dsg sgf sgp sgm gsm: gray scale mode - 00: 65,536 color mode (initial status) - 01: 4,096 color mode* (refer to ?data format select (60h/61h)?) - 10: 256 color mode* - 11: 256 color mode* * in the 256 color mode with 16-bit data bus mode and 4,096 color mode with 8-bit data format b, the address is counted as burst mode enable. so, in this case, refer to notes of burst mode at page 39. dsg: duty adjust setting - 0: dummy subgroup is one subgroup - 1: dummy subgroup is none (initial status) sgf: sub group frame inversion mode setting - 0: sg frame inversion off - 1: sg frame inversion on (initial status) sgm: sub group inversion mode setting - 0: sg inversion off - 1: sg inversion on (initial status) sgp: sub group phase mode setting - 00: same phase in all pixels - 01: different phase by 1pixel-unit - 10: different phase by 2pixel-unit (initial status) - 11: different phase by 4pixel-unit row vector mode set (32h) setting row function. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00110010 001 0000 inc vec inc: row vector increment mode. this parameter set up row vector increment period db3 db2 db1 row vector increment period 0 0 0 every subgroup 0 0 1 every 2subgroup 0 1 0 every 4subgroup 0 1 1 every 8subgroup 1 0 0 every 16subgroup 1 0 1 every 16subgroup 1 1 0 every 16subgroup 1 1 1 every sub-frame (initial status) vec: row vector sequence mode - 0: r1->r2->r3->r4 -> r1? (initial status) - 1: r1->r3->r2->r4 -> r1...
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 40 n-block inversion set (34h) this instruction set up n block inversion for ac driving. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00110100 001 fim fip 0 n-block inversion fim: forcing inversion mode fim = 0: forcing inversion off fim = 1: forcing inversion on (initial status) fip: forcing inversion period fip = 0: forcing inversion period is one frame (initial status) fip = 1: forcing inversion period is two frame n-block inversion: this parameter indicates the basic period of polarity inversion. the whole period of polarity inversion is decided by fim, fip and this parameter. (initial status: 01101) db7 db6 db5 db4 ? db0 polarity inversion period x x x 0 every frame 0 x x 1 every 1 block ::: : : 0 x x 31 every 31 blocks 1 0 x 1 every 1 block and every frame ::: : : 1 0 x 31 every 31 blocks and every frame 1 1 x 1 every 1 block and every 2 frames ::: : : 1 1 x 31 every 31 blocks and every 2 frames frame frequency control (36h) this instruction controls the internal frame frequency. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00110110 001 0000000lfs lfs: low frame frequency set for low power consumption. lfs = 0 : low frequency set off (initial status) lfs = 1 : low frequency set on note: ffr @(lfs=1) = ffr @(lfs=0) / 2
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 41 256 color mode palettes at 256-color mode, the instruction and parameter below set each gray scale level of the red/green/blue. gray scale level is determined by gs data. red palette (38h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111000 0 0 0 gs data ?000? to ram data 0 0 0 gs data ?001? to ram data 0 0 0 gs data ?010? to ram data 0 0 0 gs data ?011? to ram data 0 0 0 gs data ?100? to ram data 0 0 0 gs data ?101? to ram data 0 0 0 gs data ?110? to ram data 001 0 0 0 gs data ?111? to ram data green palette (3ah) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111010 0 0 gs data ?000? to ram data 0 0 gs data ?001? to ram data 0 0 gs data ?010? to ram data 0 0 gs data ?011? to ram data 0 0 gs data ?100? to ram data 0 0 gs data ?101? to ram data 0 0 gs data ?110? to ram data 001 0 0 gs data ?111? to ram data blue palette (3ch) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111100 0 0 0 gs data ?00? to ram data 0 0 0 gs data ?01? to ram data 0 0 0 gs data ?10? to ram data 001 0 0 0 gs data ?11? to ram data
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 42 initial value for each palette initial gray scale level gray scale data red green blue 000 0 0 0 001 8 16 12 010 12 24 20 011 16 32 31 100 20 40 - 101 24 48 - 110 28 56 - 111 31 63 - the relationship between gray scal e level and ram data for red/blue ram data ram data db4 db3 db2 db1 db0 gs level db4 db3 db2 db1 db0 gs level 00000 0 10000 16 00001 1 10001 17 00010 2 10010 18 00011 3 10011 19 00100 4 10100 20 00101 5 10101 21 00110 6 10110 22 00111 7 10111 23 01000 8 11000 24 01001 9 11001 25 01010 10 11010 26 01011 11 11011 27 01100 12 11100 28 01101 13 11101 29 01110 14 11110 30 01111 15 11111 31
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 43 the relationship between gray scale level and gray scale data for green gs data gs data db5 db4 db3 db2 db1 db0 gs level db5 db4 db3 db2 db1 db0 gs level 000000 0 100000 32 000001 1 100001 33 000010 2 100010 34 000011 3 100011 35 000100 4 100100 36 000101 5 100101 37 000110 6 100110 38 000111 7 100111 39 001000 8 101000 40 001001 9 101001 41 001010 10 101010 42 001011 11 101011 43 001100 12 101100 44 001101 13 101101 45 001110 14 101110 46 001111 15 101111 47 010000 16 110000 48 010001 17 110001 49 010010 18 110010 50 010011 19 110011 51 010100 20 110100 52 010101 21 110101 53 010110 22 110110 54 010111 23 110111 55 011000 24 111000 56 011001 25 111001 57 011010 26 111010 58 011011 27 111011 59 011100 28 111100 60 011101 29 111101 61 011110 30 111110 62 011111 31 111111 63
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 44 entry mode set (40h) setting internal function mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01000000 001 0000hlmdix/yrmw hl: when gsm is 10 or 11 (256 color mode), exchange higher and lower byte in 16-bit data bus mode only for ?display data write/read? hl = 0: not exchanged status (initial status) hl = 1: exchanged status mdi: memory data inversion setting for low power consumption. mdi = 0: memory data inversion off (initial status) mdi = 1: memory data inversion on x/y: memory address counter mode setting x/y = 0: y address counter mode (initial status) x/y = 1: x address counter mode rmw: read modify write mode on/off select rmw = 0: read modify write off (initial status) rmw = 1: read modify write on. when this mode is on, x(y) address of on-chip display ram is not increment in reading display data but in writing display data. x address area set (42h) this instruction and parameter set up the x addr ess areas of the on-chip display data ram. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01000010 x start address set (initial status = 00h) 001 x end address set (initial status = a1h) the current x address of the on-chip display data ram is the x start address by setting this instruction. in x address count mode (x/y = ?h?), the x address is increased from x start address to x end address. when x address is equal to the x end address, the y address is increased by 1 and the x address returns to x start address. the x start and x end addresses must be set as a pair and x start address must be less than x end address. data bus memory display data write display data read display data write display data read 00h 00h 00h ffh 00h 00h ffh 00h
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 45 y address area set (43h) this instruction and parameter set up the y address areas of the on-chip display data ram . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01000011 y start address set (initial status = 00h) 001 y end address set (initial status = 83h) the current y address of the on-chip display data ram is the y start address by setting this instruction. in y address count mode (x/y = ?l?), the y address is in creased from y start address to y end address. when y address is equal to the y end address, the x address is increased by 1 and the y address returns to y start address. the y start and y end address must be set as a pair and y start address must be less than y end address. ram skip area set (45h) this instruction and parameter set up the x addr ess areas of the on-chip display data ram. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01000101 001 000000 rsk rsk : ram skip function on/off set - rsk = 00 : no skip - rsk = 01 : y address 40h - 43h skip - rsk = 10 : y address 3ch - 47h skip - rsk = 11 : reserved ram skip area set ram skip area set can skip a part of ram y-address area. after setting ram skip area, y-address count skip this area and count. in other words, y address after skip area is changed into y address which added a part for skip area. memory data input display area skip area x-address area y-address area
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 46 display off (50h) turn the display off(initial status). when display is off, all segment and common output are vss level. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 001 0 1010000 function and pin condition at display off function/pin condition dc/dc booster(1?st,2?nd,3?rd) on(operate) seg and com outputs vss display on (51h) turns the display on. in case of being standby mode, this instruction does no t work. this instruction is executed after standby mode off. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00101010001 function and pin condition at display on function/pin condition dc/dc booster(1?st,2?nd,3?rd) on(operate) com outputs +vr or vm or -vr seg outputs v1 or vss specified display pattern set (53h) this instruction sets the specified display pattern. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01010011 001 000000 sdp sdp : specified display pattern set - sdp = 00 : normal display - sdp = 01 : reverse display : display data reversing mode setting without the contents of the display ram - sdp = 10 : whole display pattern becomes off regardless of the ram data. - sdp = 11 : whole display pattern becomes on regardless of the ram data.
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 47 partial display mode set (55h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01010101 001 000000pdmpt pt: partial display on/off - pt = 0: partial display off = normal mode (initial status) - pt = 1: partial display on pdm: partial display mode set - pdm = 0: partial mode 0 : duty ratio is same as normal display mode(initial status) - pdm = 1: partial mode 1 : duty ratio is changed from normal display mode (dsg = 0 : 69 line fixed(including 1 dummy subgroup), dsg = 1 : 66 line fixed(no dummy subgroup)) applied parameter in pdm0 and pdm1 are summarized as below pdm contrast duty bias dc-dc select osc pck 0 contrast control(1) normal bias(1) dc(1) osc1-osc2 div(1) 1 contrast control(2) 1/69 bias(2) dc(2) osc3-osc4 div(2) operation in partial display mode 0 (pdm=0) on scanning except partial display area - seg output select v0 or v1 level depend on ?fr? value. refer to page50. - all of com output is fixed vm level. on scanning partial display area - it is equal to be in normal mode operation in partial display mode 1 (pdm=1) display area is from partial start line to partial end line. (com driver output is fixed vm except di splay area, only max69 line output com signal. on scanning except partial display area - seg output select v0 or v1 level depend on ?fr? value. refer to page50. - all of com output is fixed vm level. on scanning partial display area - it is equal to be in normal mode display area partial start line partial end line n line pdm 0 partial start line m line 69 line fix pdm 1 no display area : no com scanning field (com = vm fixed) except partial display area : com timing is existing, but com = vm fixed partial display area : real display field partial end line
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 48 partial display mode0 item partial display area ou t of partial display area duty same as normal display mode bias same as normal display mode ( bias(1) setting ) contrast same as normal display mode ( contrast(1) setting ) oscillator same as normal display mode ( osc1 ? osc2 ) seg output level same as normal mode (v1,v0) depends on internal ?fr? signal see page 50 com output level same as normal mode (+vr,vm,-vr) vm fixed partial display mode1 item partial display area out of partial display area out of display area duty 1/69duty bias bias(2) setting contrast contrast(2) setting oscillator ( osc3 ? osc4 ) setting value seg output level same as normal mode (v1,v0) depends on ?fr? signal see page 50 - com output level same as normal mode (+vr, vm, -vr) vm fixed vm fixed in case of com 6 to com11 partial display

normal display mode partial display mode 1 +vr vm -vr
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 49 partial display start line set (56h), partial display end line set(57h) these 2 instructions set the partial display area and it is possible to display a part. partial display start line set (56h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01010110 001 partial start line partial display end line set (57h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01010111 001 partial end line parameter set appoints display line number. at pdm 0, parameter size is able to be in a number of display lines. but that is not able to be over max 69 line at pdm 1. partial end line must set bigger number than partial start line. line 0 line 1 com 0 com 1 line 2 line 3 com 2 com 3 line 158 line 159 com 158 line 160 line 161 com 159 com 160 com 161 : : :
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 50 example of segment voltage in non-display area area scroll set (59h) this instruction sets up area scroll field (start line, end line, lower fixed line number), and it is possible to make screen to display as partial scroll field. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01011001 000000 scm scroll area start line scroll area end line 001 lower fixed number scm: scroll mode setting db1 db0 mode 0 0 entire display(initial status) 0 1 upper scroll display 1 0 lower scroll display 1 1 center scroll display com partial display vm subframe +vr vm -vr v1 vm v0 addressing duty display off internal polarity counter (fr) v0 v1 v0 v1 v0 v1 v1 v0 v1 v0 vm vm vm 012 0 3 nn+1 seg frame
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 51 entire display upper display lower display center display scroll start line set (5ah) this instruction and parameter set up scroll start line. on this instruction, scroll start line becomes the first of area scroll field. scroll operation is occurred every issue of this instruction. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 01011010 001 scroll start line -dln : 2?b10 (1/162 duty) -scm : 2?b11 (center display mode) -scroll area start line : 6 -scroll area end line : 152 -lower fixed number : 9 -scroll start line : 40 upper fix com6 com161 com0 scroll area upper fix scroll display lower fix xadr=6 xadr=0 xadr=153 xadr=161 ram address. com153 com0 com6 com161 com153 lower fix addr0 addr5 addr40 addr153 addr161 addr152 addr6 a ddr39 xadr=40
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 52 data format select (60h/61h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0010110000dfs dfs: 4,096 color mode data format select - 0 : 4,096 color data format a (initial status) 8 bit mode : db[7:0] : xxxxrrrr (1?st write) db[7:0] : ggggbbbb(2?nd write) 16 bit mode : db[15:0] :xxxxrrrrggggbbbb (12 bit) - 1 : 4,096 color data format b 8 bit mode : db[7:0] : rrrrgggg(1?st write) db[7:0] : bbbbrrrr (2?nd write) db[7:0] : ggggbbbb(3?rd write) 16 bit mode : db[15:0] :rrrrggggbbbbxxxx (12 bit) normal mode normal mode partial mode 0 scroll mode scroll/partial mode 0 set partial start line set partial end line set partial mode 0 set scroll mode set scroll area start line set scroll area end line set lower fixed line no. set scroll start line set scroll mode set scroll area start line set scroll area end line set lower fixed line set scroll start line set partial start line check busy flag set partial end line set partial mode 0 release partial mode set scroll mode set scroll area start line set scroll area end line set lower fixed line no. set scroll start line set scroll mode set scroll area start line set scroll area end line set lower fixed line no. set scroll start line release partial mode
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 53 display data write/read d/i wrb rdb db15 ~ db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 display ram write in data 1 1 0 display ram read out data gsm = 00(65,536 color mode) (1) 16bit access mode 1514131211109876543210 1?st cycle r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 2?nd cycle r4r3r2r1r0g5g4g3g2g1g0b4b3b2b1b0 (2) 8bit access mode 76543210 1?st cycle r4 r3 r2 r1 r0 g5 g4 g3 2?nd cycle g2g1g0b4b3b2b1b0 3?rd cycle r4 r3 r2 r1 r0 g5 g4 g3 4?th cycle g2g1g0b4b3b2b1b0 gsm = 01(4,096 color mode) (1) 16bit access mode 1514131211109876543210 1?st cycle x x x x r3 r2 r1 r0 g3 g2 g1 g0 b3 b2 b1 b0 2?nd cycle x x x x r3r2r1r0g3g2g1g0b3b2b1b0 (2) 8bit access mode 76543210 1?st cycle x x x x r3 r2 r1 r0 2?nd cycle g3 g2 g1 g0 b3 b2 b1 b0 3?rd cycle x x x x r3 r2 r1 r0 4?th cycle g3 g2 g1 g0 b3 b2 b1 b0 gsm = 10 or 11 (256 color mode) (1) 16bit access mode 1514131211109876543210 1?st cycle r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0 2?nd cycle r2r1r0g2g1g0b1b0r2r1r0g2g1g0b1b0 (2) 8bit access mode 76543210 1?st cycle r2 r1 r0 g2 g1 g0 b1 b0 2?nd cycle r2 r1 r0 g2 g1 g0 b1 b0 3?rd cycle r2 r1 r0 g2 g1 g0 b1 b0 4?th cycle r2 r1 r0 g2 g1 g0 b1 b0
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 54 status read d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 bsy x/y oprt pdm pt stb rev dp this instruction indicates the internal status of the s6b33b2. dp: ( 0 : display off status, 1 : display on status ) rev: ( 0 : display image non-reversing, 1 : display image reversing ) stb: ( 0 : standby mode off status, 1 : standby mode on status ) pt: ( 0 : partial display mode off status, 1 : partial display mode on status ) pdm: ( 0 : partial display mode 0, 1 : partial display mode 1 ) oprt: (0: otp mode non-protection status, 1: otp mode protection status) x/y: ( 0 : y-address count mode, 1 : x-address count mode ) bsy: ( 0 : no busy, 1 : busy ) set display data length (fch) this instruction is only used in 3-pin spi mpu interf ace mode(ps=?l?, mpu[1]=?l?). it consists of two continuous commands, the first byte control the data direction(write mode only) and inform the lcd driver the second and third bytes will be number of data bytes will be write. when di is not used, the display data length instruction is used to indicate that a specified number of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 11111100 number of display data upper 8bits (ddl_h) 001 number of display data lower 8bits (ddl_l)
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 55 otp mode on (ebh) this command is used to turn otp mode on. (initial status) rs rw_wr db7 db6 db5 db4 db3 db2 db1 db0 0011101011 otp mode off (eah) this command is used to turn otp mode off rs rw_wr db7 db6 db5 db4 db3 db2 db1 db0 0011101010 offset volume set (edh) this command is used to set offset value x (-32 to +31) to electronic volume by 2s complement. rs rw_wr db7 db6 db5 db4 db3 db2 db1 db0 0011101101 0 0 0 oprt p15 p14 p13 p12 p11 p10 oprt : otp mode protection bit 0 : otp cell is able to be programmed 1 : otp cell isn?t able to be programmed p15 p14 p13 p12 p11 p10 offset volume(x) 0 1 1111 31 : : :::: 0 0 0001 1 0 0 0000 0 1 1 1111 -1 ::::: : 1 0 0000 -32 otp write enable (efh) this command is used to write offset value (ov) into eprom cells. rs rw_wr db7 db6 db5 db4 db3 db2 db1 db0 0011101111
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 56 test mode1 (ffh) this instruction is for testing ic. user is not permitted to access. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111111 test mode2 (feh) this instruction is for testing ic. user is not permitted to access. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111110 test mode3 (fdh) this instruction is for testing ic. user is not permitted to access. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111101 test mode4 (fbh) this instruction is for testing ic. user is not permitted to access. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111011 test mode5 (fah) this instruction is for testing ic. user is not permitted to access. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111010 test mode6 (f9h) this instruction is for testing ic. user is not permitted to a ccess. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111001 test mode7(f8) this instruction is for testing ic. user is not permitted to access. if access, have to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 00111111000
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 57 instruction parameter table 16. instruction parameter instruction hex para. db7 db6 db5 db4 db3 db2 db1 db0 00 0 0 0 0 ext osc oscillation mode set 02h 1 ** * * * * 0 0 0 0 dln 0 sdir swp 0 driver output mode set 10h 1 **00* 0 0 0 000 0 dc(2) dc(1) dc-dc set 20h 1 00 0 0 0 0 0 0 00 bias(2) 0 0 bias(1) bias set 22h 1 0* 00 * * 0 0 0 0 div(2) 0 0 div(1) dcdc clock division set 24h 1 **10* * 1 0 0 0 0 0 amp dcdc3 dcdc2 dcdc1 dcdc and amp on/off set 26h 1 ** * *0 0 0 0 00 0 0 0 0 tcs temperature compensation set 28h 1 ** * * * * 0 0 contrast control value in normal and partial display mode0(0 to 255) contrast control (1) 2ah 1 00 0 0 0 0 0 0 contrast control value in partial display mode 1(0 to 255) contrast control(2) 2bh 1 00 0 0 0 0 0 0 0 gsm dsg sgf sgp sgm addressing mode set 30h 1 *0011 1 0 1 0 0 0 0 inc vec row vector mode set 32h 1 ** * *1 1 1 0 fim fip 0 n-block inversion n-line inversion set 34h 1 10 * 0 1 1 0 1 00 0 0 0 0 0 lfs frame frequency control 36h 1 ** * * * * * 0 0 0 0 0 hl mdi x/y rmw entry mode set 40h 1 ** * * * 0 0 0 x start address set 00 0 0 0 0 0 0 x end address set x-address area set 42h 2 10 1 0 0 0 0 1 y start address set 00 0 0 0 0 0 0 y end address set y-address area set 43h 2 10 0 0 0 0 1 1 00 0 0 0 0 rsk ram skip area set 45h 1 ** * * * * 0 0 number of display data ddl_h set display data length fch 2 number of display data ddl_l 00 0 0 0 0 sdp specified display pattern set 53h 1 ** * * * * 0 0 00 0 0 0 0 pdmpt partial display mode set 55h 1 ** * * * * 0 0 partial start line partial display start line set 56h 1 00 0 0 0 0 0 0 partial end line partial display end line set 57h 1 00 0 0 0 0 0 0
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 58 table 16. instruction parameter (continued) instruction hex para. db7 db6 db5 db4 db3 db2 db1 db0 000000 scm ******00 scroll area start line 00000000 scroll area end line 10100001 lower fixed number area scroll mode set 59h 4 00000000 scroll start line scroll start line set 5ah 1 00000000 11101101 offset volume set edh 1 ***00000
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 59 reset operation when rstb becomes ?l?, following procedure is occurred. - x start address: 0, x end address: 161, - y start address: 0, y end address: 131 - display off - read modify write mode off - function mode set mdi = 0: memory data inversion off osc = 0: oscillator off ext = 0: internal oscillator mode rev = 0: reversing mode off x/y = 0: y-address count mode standby mode on - dcdc clock division set div(1) = 10: fpck = fosc/16x div(2) = 10: fpck = fosc/16x -duty set display duty = 00: 1/132 duty -dc-dc select dc(1) = 0: x1 step-up dc(2) = 0: x1 step-up - bias set bias(1) = 0h: 1/4 bias bias(2) = 0h: 1/4 bias - dc/dc and amp on/off set amp =0: built-in op-amp off dcdc1 =0: built-in 1?st booster off dcdc2 =0: built-in 2?nd booster off dcdc3 =0: built-in 3?rd booster off - n-block inversion fim =1: forcing inversion on fip =0: forcing inversion period in one frame n-block inversion = 0dh: 13 block inversion - frame frequency control lfs =0: low frequency set off - partial display mode pt = 0: partial display mode off - partial display area set partial start line = 00h partial end line = 00h -area scroll set mode = 00h : entire display scroll mode area start line: 00h area end line: a1h lower fixed line number: 00h - scroll start line set scroll start line: 00h - addressing mode set gsm=00: 65,536 color mode dsg = 1: no dummy subgroup sgf = 0: sg frame inversion off sgm = 1: sg reverse mode on sgp=10: different phase by 2pixel-unit - row vector mode set inc =111: increment every sub-frame vec=0: r1->r2->r3->r4->r1->?
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 60 power on/off seqence power on sequence power on reset waiting for releasingreset standby mode off busy flag check or waiting for osc on dcdc1 on amp on dcdc2 on no busy busy set various registers and ram data if needed (xs,xe,ys,ye,mdi,ext,rev,xy,div,dln,bias,dc, fim,fip,n-block,pt,pdm,smod,dsg,gsm,sgf, sgm,sgp,inc,vec, display data) display on dcdc3 on
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 61 power off sequence standby on ( dcdc3 off dcdc2 off amp off dcdc1 off osc off ) waiting for discharge power off display off
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 62 specifications absolute maximum ratings item symbol rating unit supply voltage range vdd3 -0.3 to +4.0 v lcd supply voltage range | vcc ? vee| 22 v input voltage range vin - 0.3 to vdd +0.3 v operating temperature range t opr -30to+70 c storage temperature range t str -55to+150 c operating voltage item symbol min. typ. max. unit supply voltage (1) vdd3 1.8 - 3.3 v supply voltage (2) 2vr 4.0 - 20 v supply voltage (3) vin 2.4 3.0 3.6 v
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 63 dc characteristics (1) (vss = 0v, v dd3 = 1.8 to 3.3v, ta = -30 to 70 c) item symbol condition min typ max unit remarks operating voltage vdd3 1.8 3.3 v vdd3 operating voltage vin1 2.4 - 3.6 v vin1,vin1a operating voltage vin2 2.4 - 7.2 v operating voltage vin45 2.4 - 7.2 v vout45 1/4 bias 1.5 - 3.0 1/5 bias 1.33 - 2.67 1/6 bias 1.67 - 3.33 operating voltage dc2in 1/7 bias 1.5 - 3.0 vdc2out operating voltage 2vr 2vr = |(+vr)- (-vr)| 4.0 - 20 v +vr, -vr vm 1.0 2.0 v vmout vcc 5.0 12.0 v vrp driving voltage input range vee external power supply mode -3.0 -8.0 v vrn high v ih 0.8vdd - vdd input voltage low v il vss - 0.2vdd v high v oh i oh = 0.5ma 0.8vdd - vdd output voltage low v ol i ol = 0.5ma vss - 0.2vdd v input leakage current i il vin = vdd or vss -1.0 - +1.0 a output leakage current i oz vin = vdd or vss -3.0 - +3.0 a normal or partial 0 f osc1 r1=90kohm, (ffr=100hz target), dsg=0, 162 duty, vdd3=3v, ta=25 c 155.5 172.8 190.1 khz osc1 - osc2 oscillator frequency tolerance partial 1 f osc2 r1=300kohm, (ffr=70hz target), dsg=0, 66 duty vdd3=3v, ta=25 c 44.35 49.28 54.21 khz osc3 - osc4 normal or partial 0 f osc1 (*1) 61.44 259.2 khz osc1 - osc2 oscillator frequency range partial 1 f osc2 (*2) 29.44 88.32 khz osc3 - osc4 driving voltage input range v1 vm 2.0 1.0 - 4.0 2.0 v regulator output range reg_out reg_enb = ?l? 1.8 - 2.2 v (*1) minimum oscillator frequency range is defined at ffr=60hz and display line number=96 maximum oscillator frequency range is defined at ffr=150hz and display line number=162 (*2) minimum oscillator frequency range is defined at ffr=40hz and display line number=69 maximum oscillator frequency range is defined at ffr=120hz and display line number=69
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 64 dc characteristics (2) item symbol condition min typ max unit remarks seg r on-seg v1=3.0 v, v0=0v, ta = 25 c, iload=50ua -1.53.0 k ? segn driver output resistance com r on-com vcc=10.5 v, vm=1.5v, vee=-7.5v, ta = 2 5 c, iload=100ua -1.01.5 k ? comn normal mode vdd3=vin1=3.0v, v1=3.0v, bias(1)=1/6, dc(1)=x1.5, ta=25 c, display line=162 dsg=1 (no dummy) f osc 1=172.8khz (ffr=100hz) no load, no access, all white pattern - 750 950 ? current consumption partial1 mode idd vdd3=vin1=3.0v, v1=3.0v, bias(2)=1/5, dc(2)=x1.5, ta=25 c, 1/66 duty f osc 2=49.28khz (ffr=70hz) no load, no access, all white pattern - 300 500 ? vdd3 + vin1 * : ?idd? is determined from lowest power consumption for dc-dc converter.
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 65 dc characteristics (3) (vss = 0v, v dd3 = 1.8 to 3.3v, vin1=2.4 to 3.6v, ta = -30 to 70 c) item symbol condition min typ max unit remarks ? (+vr) isource = 80ua - - 150 mv +vr ? (v1) isource = 250ua - - 20 mv v1 ? (vm) isource,sink = 250ua - - 20 mv vm voltage shift range(*1) ? (-vr) isink = 80ua - - 150 mv -vr (*1) voltage shift means output voltage deferen ce between output curre nt = iload and no-load. refer to the following figure. (in case of source current mode) item symbol condition min typ max unit remarks tolerance of bias ratio ? (+vr)_0 ? (-vr)_0(*1) no load -100 - +100 mv +vr -vr (*1) tolerance of bias ratio definition ? (+vr)_0 = ((+vr) - vm ) ? vm / bias ? (-vr)_0 = ( vm - (-vr)) ? vm / bias no-load vx vx vy vy i=0 i=iload vshift = |vx-vy| current = i load
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 66 dc characteristics (4) (vss = 0v, v dd3 = 1.8 to 3.3v, vin1=2.4 to 3.6v, ta = -30 to 70 c) item symbol condition min typ max unit remarks temperature compensation ? vt vdd3=vin1=v1=3.0v, -20 to 70 c -0.02 - +0.02 %/ c v1 tolerance of contrast step of v1 ? vstep 3.92 7.84 11.76 mv v1 v1 3.95 4.00 4.05 v v1 contrast set = ffh vm 1.95 2.00 2.05 v vm v1 1.95 2.00 2.05 v v1 voltage range ? v1 ? vm contrast set = 00h vm 0.95 1.00 1.05 v vm condition item load current voltage range max unit ref ||+vr-vm| -|vm -(-vr)|| i load = +100ua (+vr) i load = -100ua (-vr) 150 mv fig.1 a i load = +100ua ( v1, vm ) offset voltage ||v1-vm| -|vm-v0|| b i load = +100ua (+vr) i load = -100ua (-vr) +vr=5.0~12.0 v v1=2.0~4.0v vm=1.0~2.0v -vr=-3.0~-8.0 v 50 mv fig.2 +vr fig. 1: offset voltage definition (+vr,vm,-vr) vx |vx-vy| < 150mv vm -vr vy +100ua -100ua v1 va |va-vb| < 50mv vm v0 vb +100ua (both case a and b) -100ua (case b) +100ua (case a) fig. 2: offset voltage definition (v1,vm,v0)
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 67 dc characteristics (5) (vss = 0v, v dd3 = 1.8 to 3.3v, vin1=2.4 to 3.6v, ta = -30 to 70 c) range item min max v1out 2.0 v 4.0 v (dc(1) and dc(2) = x2) (*1) vmout 1.0 v 2.0 v (dc(1) and dc(2) = x2) (*2) voltage level dc2out 1.33v (1/5 bias, v1out = 2v) 3.33v (dc(1) and dc(2) = x2) (*3) (1/6 bias, v1out = 4v) if v1out input voltage is set over vin45, v1out output voltage must be clipped near vin45. in this case, v1out output level must not be unstable. refer to fig.1 v1out vin45 delta v > 0.3 v (external vin45) delta v (*1) this definition is shown as below vin45 v1out output vin45 vin45 - delta v fig. 1 v1out input delta v > 0.5 v (vin45 = vout45) if vmout input voltage is set over vin1, vmout output voltage must be clipped near vin1. in this case, vmout output level must not be unstable. refer to fig.2 vmout vin1 delta v > 0.3 v delta v (*2) this definition is shown as below vin1 vmout output vin1 vin1 - delta v fig. 2 vmout input if dc2out input voltage is set over vin2, dc2out output voltage must be clipped near vin2. in this case, dc2out output level must not be unstable. refer to fig.3 dc2out vin2 delta v > 0.3 v (external vin2) delta v (*3) this definition is shown as below vin2 dc2out output vin2 vin2 - delta v fig. 3 dc2out input delta v > 0.5 v (vin2 = vout45)
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 68 ac characteristics read / write characteristics (8080-series mpu) db0 to db7 (write) db0 to db7 (read) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw l80(r) , t pwl80(w) t cy80 t ah80 t as80 /rd, /wr /cs1 (cs2) d/i t pwh80(r) , t pw h80(w) ** t pwl80(w) and t pwl80(r) is specified in the overlapped period when cs1b is low (cs2 is high) and /wr(/rd) is low. figure 25. parallel interface (8080-series mpu) timing diagram table 17. ac characteristics (8080-series parallel mode) (vdd3 = 1.8 to 3.3v, ta = -30 to +70 c) min. item signal symbol condition 3.3v 1.8v max. (3.3v/1.8v) unit address setup time address hold time d/i t as80 t ah80 0 0 0 0 - - ns system cycle time t cy80 150 360 - ns pulse width low for write pulse width high for write wrb (wrb) t pwlw t pwhw 50 30 100 75 - - ns pulse width low for read pulse width high for read rdb (rdb) t pwlr t pwhr 50 30 100 75 - - ns data setup time data hold time t ds80 t dh80 5 28 10 54 - - ns - 60 / 120 read access time output disable time db0 to db15 t acc80 t od80 cl = 100 pf - 50 / 100 note: *1. the input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (t cy80 -t pwlw -t pwhw ) for write, (tr + tf) < (t cy80 -t pwlr -t pwhr ) for read
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 69 read / write characteristi cs (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t ewh68(r) , t ewh68(w) t cy68 t ah68 t as68 db0 to db7 (write) e /cs1 (cs2) d/i,r/w db0 to db7 (read) t ewl68(r) , t ewl68(w) ** t ewh68(w) and t ewh68(r) is specified in the overlapped period when /cs1 is low (cs2 is high) and e is high. figure 26. parallel interface (6800-series mpu) timing diagram table 18. ac characteristics (6800-series parallel mode) (v dd3 = 1.8 to 3.3v, ta = -30 to +70 c) min. item signal symbol condition 3.3v 1.8v max. (3.3v/1.8v) unit address setup time address hold time d/i r/w t as68 t ah68 0 0 0 0 - - ns system cycle time t cy68 150 360 - ns enable width high for write enable width low for write rdb (e) t ewhw t ewlw 50 30 100 75 - - ns enable width high for read enable width low for read rdb (e) t ewhr t ewlr 50 30 100 75 - - ns data setup time data hold time t ds68 t dh68 5 28 10 54 - - ns - 60 / 120 read access time output disable time db0 to db15 t acc68 t od68 c l = 100 pf - 50 / 100 note: *1. the input signal rise time and fall time (tr, tf) is specified at 10 ns or less. (tr + tf) < (t cy68 -t ewhw -t ewlw ) for write, (tr + tf) < (t cy68 -t ewhr -t ewlr ) for read
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 70 serial data interface timing /cs1 sdi d/i scl t csh t sdh t sah t scyc t css t sds t sas t slw t shw t f 0.1v dd 0.1v dd t r 0.9v dd 0.1v dd 0.9v dd 0.1v dd (cs2) table 19. serial data interface timing (v dd3 = 1.8 to 3.3v, ta = -30 to +70 c) item signal symbol condition min. max. unit scl cycle time scl t scyc 120 - ns scl high pulse width scl t shw 60 - ns scl low pulse width scl t slw 60 - ns sdi setup time sdi t sds 60 - ns sdi hold time sdi t sdh 60 - ns d/i setup time d/i t sas 60 - ns d/i hold time d/i t sah 60 - ns chip select setup time cs1b (cs2) t css 60 - ns chip select hold time cs1b (cs2) t chs 60 - ns
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 71 reset input timing /rst internal status t rw t r reset complete during reset figure 27. reset i nput timing diagram table 20. ac characteristics (reset mode) (v dd3 = 1.8 to 3.3v, ta = -30 to +70 c) item signal symbol condition min. max. unit reset low pulse width rstb t rw 1000 - ns reset time - t r - 1000 ns series specifications product code temp. coefficient tcs register set * s6b33b2a01-b0cy 0.00%/ c 00 S6B33B2A02-B0CY -0.05 %/ c 01 s6b33b2a03-b0cy -0.10 %/ c 10 s6b33b2a04-b0cy -0.15 %/ c 11 note : in case of s6b33b2a01-b0cy, sec guarantees only 0.00%/ c, not ?0.05 and ?0.10, -0.15%/ c. in case of S6B33B2A02-B0CY, sec guarantees only -0.05%/ c, not ?0.00 and ?0.1, -0.15%/ c. in case of s6b33b2a03-b0cy, sec guarantees only -0.10%/ c, not ?0.00 and ?0.05, -0.15%/ c. in case of s6b33b2a04-b0cy, sec guarantees only -0.15%/ c, not ?0.00 and ?0.05, -0.10%/ c.
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 72 system application diagram internal power mode external components name device r1,r2 resistors c1,c2,c3 capacitors d1 schottky barrier diode rd discharge resistor values of external components item capacitance c1 1.0 to 4.7 f c2 1.0 to 2.2 f c3 1.0 to 2.2 f d1 vforward = max. 0.3v at 1ma vreverse = min. 15v rd typ. 1m ohm note : employing rd is recommended when abnormal display occurs in recovery sequence after detaching battery. (it depends on module or panel characteristics.) maximum rating voltage of capacitors item maximum rating voltage reg_out to vss 3v vout45 to vss 11v c11p to c11m 6v c12p to c12m 6v vmout to vss 3v dc2out to vss 5v v1out to vss 6v c21p to c21m 5v c22p to c22m 10v c23p to c23m 13v c24p to c24m 13v vss to vrn 13v c31p to c31m 17v vrp to vss 18v s6b33b2 osc1 osc2 osc3 osc4 r1 r2 osc5 /wr /rd db15db0 d/i /cs1 /wr /rd db15 to db0 mpu cs2 d/i /rst /cs1 cs2 c11p c11m c12p c12m c2 c2 vout45 vin45 c3 vin1, vin1a vin1 vdd3, vdd3r vdd, vddo reg_out vdd3 or reg_out c1 vees, vee v1out v1in c3 vmout vmin c3 c31p c31m c2 vrp vcc c3 v0in vss, vssa, vssb, vsso /rst c21p c21m c22p c22m c2 c2 c23m c24p c24m c2 c2 vrn c3 vin2 vin2 dc2out dc2in c3 c23p d1 rd
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 73 external power mode s6b33b2 osc1 osc2 osc3 osc4 r1 r2 osc5 /wr /rd db15 to db0 d/i / rst /cs1 /wr /rd db15 to db0 mpu cs2 d/i /rst /cs1 cs2 c11p c11m c12p c12m vdd3, vdd3r vdd, vddo reg_out vdd3 or reg_out c vout45 vin45 vin1, vin1a vin1 c21p c21m c22p c22m c23p c23m c24p c24m vrn vees, vee vin2 vin 2 dc2out dc2in v1out v1in vmout vmin c31p c31m vrp vcc v1in vmin ve e vc c v0in vss, vssa, vssb, vsso
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 74 otp calibration mode sequence for setting the modified electronic volume - next figure is a block diagram of sequence for setting the modified electronic volume. otp calibration 6bit offset (otp_ov) inst calibration 6bit offset (inst_ov) mux electronic volume 8bit level (ev) adder 0 1 otp_mode on/off modified ev 8bit level (mev) otp writing process figure 28. sequence for setting the modified electronic volume initially, otp cell is not programmed and has 6'b00000 val ue. when the external reset is applied, otp mode is on. mev is ev + otp_ov. since otp_ov is 6'b00000, mev is ev. for v1out calibration the instruction "otp mode off" is executed, and then mev is ev + ov and user can adjust mev value usi ng the instruction "s et offset volume register". when mev overflows or underflows, mev will be satura ted. repeat this step unt il end of the calibration. if v1out calibration is suitable, otp writing process is executed, and then otp cell is programmed and otp_ov is programmed with ov. finally, v1out calibration process is finished. again, when the external reset is applied, otp mode is on. mev is ev + otp_ov. accordingly mev is t he ev that has always the offset with otp_ov value. however, if programmed otp_ov is unlike, the instruction "otp mode off" can be executed and then mev will be ev + ov. accordingly ov can be adjusted with instructions although otp cell is programmed.
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 75 eprom cell structure otp (one time programmable) has been implemented on the s6b33b2. the eprom stores the offset volume for v1out calibration after the device has been assembled and calibrated on a lcd module. for otp programming, otpd pin and otpg pin are used. these pins should be available to on the module glass by ito. the otp block of the s6b33b2 consists of 7 bits. 1 bit is used for otp mode protection bit (oprt), and 6 bits are used for v1out calibration (ov5~ov0). oprt can be read or written automatically in this lsi. eprom block msb lsb oprt ov5 ov4 ov3 ov2 ov1 ov0 description oprt : the offset volume(ov) can be wri tten to eprom cells only when oprt bit = ?0? ov5~ov0 : the ov is used for calibrating the v1out voltage as an offset to the ev register value. v1out calibration flow v1out may be calibrated with otp in the following order.(ex : ev = 32, ov=-3) step rs rw db7 db6 db5 db4 db3 db2 db1 db0 description 1. apply external reset (otp data read) 0000101010 or1 2. 000010000 0 set contrast control 1 or 2 by using instruction (ev = 32) 3. 001110101 0 otp mode off by using the instruction 001110110 1 4. 000011110 1 set offset volume by using the instruction (ov = -3) 5 repeat step 4. until the end of the calibration 6. apply programming voltages for otp programming (otpg=12.5v,otpd=10) 7. 000010110 1 standby on by using the instruction. 8 001110111 1 otp write enable (only available when oprt= 0) 9 apply external reset 10. cut off programming voltages for otp programming (otpg,otpd) after the external reset, the calibrated data are automati cally transferred to the 6-bit reference voltage control register. *step 6, 7, 8, 9 are otp_writing process. *otp_writing process is available when oprt is zero (if oprt = 1, otp cell could not be programmed).
132 rgb segment & 162 common driver for 65,536 color stn lcd s6b33b2 ver 1.5 76 voltages and waveforms for otp programming otpg otpd po w e r save on otp write ena bl e resetb 10v * 12.5v * otp write mode t1 t2 t3 figure 29. voltages and waveforms for otp programming (otp writing process) * note : voltages for otpg and otpd may be changed. specific timings (t1~t3) timing min max t1,t2 100us - t3 100ms 300ms
s6b33b2 ver 1.5 132 rgb segment & 162 common driver for 65,536 color stn lcd 77 revision history s6b33b2 specification revision history version content date 0.0 original oct. 2002 0.1 added otp calibration mode nov.2002 0.2 added pad coordinate and pad configuration and pad dimension jan.2003 0.3 modify pad name(p6,7) : dummy<9:8> -> dmy_test<1:0>, dummy<14:13> -> dmy_test<3:2> add the dmy_test pin description (p14) add the series specifications (p71) add the discharge resistor at t he system application diagram (p72) jun.2003 0.4 modify the read status flag (p54) july.2003 1.0 definition of tbd items change dln initial value (p29) nov.2003 1.1 modify the ac characteristics (p68,69 ) jan.2004 1.2 modify the ac characteristics (data hold time, p68/p69) jan.2004 1.3 add the condition of oscillator frequency tolerance (additional condition: vdd3/ta, p63) jan.2004 1.4 modify the otp specific timings (t3 max. : 2s -> 300ms, p76) feb.2004 1.5 correct the tolerance of contrast step of v1. (p66) mar.2004

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